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june 2010 i ? 2010 actel corporation igloo plus low power flash fpgas with flash*freeze technology features and benefits low power ? 1.2 v to 1.5 v core voltage support for low power ? supports single-voltage system operation ? 5 w power consumption in flash*freeze mode ? low power active fpga operation ? flash*freeze technology enables ultra-low power consumption while maintaining fpga content ? configurable hold previous state, tristate, high, or low state per i/o in flash*freeze mode ? easy entry to / exit from ultra-low power flash*freeze mode feature rich ? 30 k to 125 k system gates ? up to 36 kbits of true dual-port sram ? up to 212 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal, flash-based cmos process ? live-at-power-up (lapu) level 0 support ? single-chip solution ? retains programmed design when powered off ? 250 mhz (1.5 v systems) and 160 mhz (1.2 v systems) system performance in-system programming (isp) and security ? secure isp using on-chip 128-bit advanced encryption standard (aes) decryption via jtag (ieee 1532?compliant) ? ? flashlock ? to secure fpga contents high-performance routing hierarchy ? segmented, hierarchical routing and clock structure advanced i/o ? 1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?4 banks per chip on all igloo ? plus devices ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v / 1.2 v ? selectable schmitt trigger inputs ? wide range power supply voltage support per jesd8-b, allowing i/os to operate from 2.7 v to 3.6 v ? wide range power supply voltage support per jesd8-12, allowing i/os to operate from 1.14 v to 1.575 v ? i/o registers on input, output, and enable paths ? hot-swappable and cold-sparing i/os ? programmable output slew rate and drive strength ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible small-footprint packages across the igloo plus family clock conditioning circuit (ccc) and pll ? ? six ccc blocks, one with an integrated pll ? configurable phase shift, multiply/divide, delay capabilities, and external feedback ? wide input frequency range (1.5 mhz up to 250 mhz) embedded memory ? 1 kbit of flashrom user nonvolatile memory ? srams and fifos with variable-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations) ? ? true dual-port sram (except 18) ? ? the aglp030 device does not support this feature. table 1 ? igloo plus product family igloo plus devices aglp030 aglp060 aglp125 system gates 30,000 60,000 125,000 typical equivalent macrocells 256 512 1,024 versatiles (d-flip-flops) 792 1,584 3,120 flash*freeze mode (typical, w) 5 10 16 ram kbits (1,024 bits) ? 18 36 4,608-bit blocks ? 4 8 secure (aes) isp ? yes yes flashrom kbits 1 1 1 integrated pll in cccs 1 ? 1 1 versanet globals 2 618 18 i/o banks 4 4 4 maximum user i/os 120 157 212 package pins cs vq cs201, cs289 vq128 cs201, cs289 vq176 cs281, cs289 notes: 1. aglp060 in cs201 does not support the pll. 2. six chip (main) and twelve quadrant global networks are available for aglp060 and aglp125. revision 11 ?
igloo plus low power flash fpgas ii revision 11 i/os per package 1 igloo plus device status igloo plus devices aglp030 aglp060 aglp125 package single-ended i/os cs201 120 157 ? cs281 ? ? 212 cs289 120 157 212 vq128 101 ? ? vq176 ? 137 ? note: when the flash*freeze pin is used to directly enable flash*free ze mode and not used as a regular i/o, the number of single- ended user i/os available is reduced by one. table 2 ? igloo plus fpgas package size dimensions package cs201 cs281 cs289 vq128 vq176 length width (mm/mm) 8 8 10 10 14 14 14 14 20 20 nominal area (mm2) 64 100 196 196 400 pitch (mm) 0.5 0.5 0.8 0.4 0.4 height (mm) 0.89 1.05 1.20 1.0 1.0 igloo plus device status aglp030 production aglp060 production aglp125 production
igloo plus low power flash fpgas revision 11 iii igloo plus ordering information notes: 1. marking information: igloo plus v2 devices do not have a v2 marking, but igloo plus v5 devices are marked accordingly. 2. "g" indicates rohs-compliant packages. supply voltage 2 = 1.2 v to 1.5 v 5 = 1.5 v only aglp125 v2 cs _ part number package type 289 i package lead count g lead-free packaging application (temperature range) blank = commercial (0c to +70c ambient temperature) i = industrial ( ? 40c to +85c ambient temperature) blank = standard packaging g= rohs-compliant packaging pp = pre-production es = engineering sample (room temperature only) 30,000 system gates aglp030 = 60,000 system gates aglp060 = 125,000 system gates aglp125 = cs = chip scale package (0.5 mm and 0.8 mm pitches) vq = very thin quad flat pack (0.4 mm pitch)
igloo plus low power flash fpgas iv revision 11 temperature grade offerings contact your local actel representative for device availability: http://www.actel.com/compa ny/contact/default.aspx . package aglp030 aglp060 aglp125 cs201 c, i c, i ? cs281 ??c, i cs289 c, ic, ic, i vq128 c, i ? ? vq176 ?c, i? notes: 1. c = commercial temperature range: 0c to 70c ambient temperature. 2. i = industrial temperature range: ?40c to 85c ambient temperature.
igloo plus low power flash fpgas revision 11 v table of contents igloo plus device family overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 igloo plus dc and swit ching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 clock conditioning circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 embedded sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 embedded flashrom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 actel safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 package pin assignments 128-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 176-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 201-pin csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 281-pin csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 289-pin csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 actel safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

revision 11 1-1 1 ? igloo plus device family overview general description the igloo plus family of flash fpgas, based on a 130 nm flash process, offers the lowest power fpga, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of advanced features. the flash*freeze technology used in igloo plus devices enables entering and exiting an ultra-low power mode that consumes as little as 5 w whil e retaining the design information, sram content, registers, and i/o states. flash*freeze technolog y simplifies power management through i/o and clock management with rapid recovery to operation mode. the low power active capability (static idle) allo ws for ultra-low power c onsumption while the igloo plus device is completely functional in the syste m. this allows the igloo plus device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. nonvolatile flash technology gives igloo plus dev ices the advantage of being a secure, low power, single-chip solution that is live at power-up (lapu). igloo plus is reprogrammable and offers time-to- market benefits at an asic-level unit cost. these features e nable designers to create high -density systems using existing asic or fpga design flows and tools. igloo plus devices offer 1 kbit of on-chip, reprogrammable, nonvolat ile flashrom storage as well as clock conditioning circuitry based on an integrated ph ase-locked loop (pll). igloo plus devices have up to 125 k system gates, supported with up to 36 kbit s of true dual-port sram and up to 212 user i/os. the aglp030 devices have no pll or ram support. flash*freeze technology the igloo plus device offers unique flash*freeze technology, allowing the device to enter and exit ultra-low power flash*freeze mode. igloo plus devi ces do not need additional components to turn off i/os or clocks while retaining t he design information, sram cont ent, registers, and i/o states. flash*freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the fi nal stages of manufacturing or in the field. the ability of igloo plus v2 devices to support a wide range of core and i/o voltages (1.2 v to 1.5 v) allows further reduction in powe r consumption, thus achieving the lowest total system power. during flash*freeze mode, each i/o can be set to the following configurations: hold previous state, tristate, or set as high or low. the availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high- pin-count packages, make igloo plus devices the best fit for portable electronics. flash advantages low power igloo plus devices exhibit power characteristics sim ilar to those of an asic, making them an ideal choice for power-sensitive applications. igloo plus devices have only a very limited power-on current surge and no high-current transition peri od, both of which occur on many fpgas. igloo plus devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 v core voltage. low dynamic power consumption, combined with low static power consumption and flash*freeze technology, gives the ig loo plus device the lowest total system power offered by any fpga.
igloo plus device family overview 1-2 revision 11 security the nonvolatile, flash-based igloo plus device s do not require a boot prom, so there is no vulnerable external bitstream that can be easily copied. igloo plus device s incorporate flashlock, which provides a unique combination of reprogr ammability and design security without external overhead, advantages that only an fpga with nonvolatile flash programming can offer. igloo plus devices (except aglp030) utilize a 128- bit flash-based lock and a separate aes key to secure programmed intellectual property and conf iguration data. in addition, all flashrom data in igloo plus devices can be encrypt ed prior to loading, using the industry-leading aes-128 (fips192) bit block cipher encryption standard. aes was adopted by the national institute of standards and technology (nist) in 2000 and replaces the 1977 des standard. igloo plus devices have a built-in aes decryption engine and a flash-based aes ke y that make them t he most comprehensive programmable logic device secu rity solution available today. igloo plus devices with aes-based security allow for secure, remote field updates over public networks such as the internet, and ensure that valuable ip remains out of the hands of system ov erbuilders, system cloners, and ip thieves. the contents of a programmed igloo plus device cannot be read back, although secure design verification is possible. security, built into the fpga fabric, is an inheren t component of the igloo pl us family. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremel y difficult. the igloo plus family, with flashlock and aes security, is unique in being highly resistant to both invasive and noninvasive attacks. your valuable ip is protected and secure, making remote isp possible. an iglo o plus device provides the most impenetrable security for programmable logic designs. single chip flash-based fpgas store their configuration informati on in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga st ructure, and no external configuration data needs to be loaded at system power -up (unlike sram-based fpgas). th erefore, flash-based igloo plus fpgas do not require system configuration compo nents such as eeproms or microcontrollers to load device configuration data. this reduces bill-of-materi als costs and pcb area, and increases security and system reliability. the igloo plus devices can be operated with a 1.2 v or 1.5 v single-voltage supply for core and i/os, eliminating the need for additional supplies while minimizing total power consumption. live at power-up the actel flash-based igloo plus devices support level 0 of the lapu classification standard. this feature helps in system component in itialization, execution of critic al tasks before the processor wakes up, setup and configuration of memory blocks, cl ock generation, and bus activity management. the lapu feature of fl ash-based igloo plus device s greatly simplifi es total system design and reduces total system cost, often el iminating the need for cpld s and clock generation plls . in addition, glitches and brownouts in system power will not corrupt the ig loo plus device's flash configuration, and unlike sram-based fpgas, the device will not have to be reloaded when system pow er is restored. this enables the reduction or complete removal of t he configuration prom, expensive voltage monitor, brownout detection, and clock generator device s from the pcb design. flash-based igloo plus devices simplify total system design and reduce cost and des ign risk while increasin g system reliability and improving system initialization time. igloo plus flash fpgas allow the user to quickly enter and exit flash*freeze mode. this is done almost instantly (within 1 s), and the device retain s configuration and data in registers and ram. unlike sram-based fpgas, the device does not need to reload configuration and design state from external memory components; instead, it retains all necessary information to resume operation immediately. reduced cost of ownership advantages to the designer extend beyond low unit cost, performance, and ease of use. unlike sram- based fpgas, flash-based igloo plus devices allo w all functionality to be live at power-up; no external boot prom is required. on-board securi ty mechanisms prevent access to all the programming information and enable secure remote updates of th e fpga logic. designers can perform secure remote in-system reprogramming to support future design iterations and field upgra des with confidence that valuable intellectual property cannot be compromised or copied. secure isp can be performed using the
igloo plus low power flash fpgas revision 11 1-3 industry-standard aes algorithm. the igloo plus fa mily device architecture mitigates the need for asic migration at higher user volumes. this ma kes the igloo plus family a cost-effective asic replacement solution, especially for applicatio ns in the consumer, networking/communications, computing, and avionics markets. firm-error immunity firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prevent in sram fpgas. the consequence of this type of error can be a complete system failure. firm errors do not exist in the configuration memory of igloo plus flash- based fpgas. once it is programmed, the flash cell configuration element of igloo plus fpgas cannot be altered by high-energy ne utrons and is therefor e immune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. advanced flash technology the igloo plus family offers many benefits, incl uding nonvolatility and reprogrammability, through an advanced flash-based, 130 nm lvcm os process with seven layers of metal. standard cmos design techniques are used to implement logic and contro l functions. the combination of fine granularity, enhanced flexible routing resources, and abundant fl ash switches allows for very high logic utilization without compromising device routability or perform ance. logic functions within the device are interconnected through a four-level routing hierarchy. igloo plus family fpgas utilize design and process techniques to minimize power consumption in all modes of operation. advanced architecture the proprietary igloo plus architecture provides granularity comparable to standard-cell asics. the igloo plus device consists of five distinct and programmable arch itectural features ( figure 1-1 on page 1-4 ): ? flash*freeze technology ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory ? ? extensive cccs and plls ? ? advanced i/o structure the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. the versatility of the igloo plus co re tile as either a three-input lookup table (lut) equivalent or a d-flip-flop/latch with enable allows fo r efficient use of the fpga fabric. the versatile capability is unique to the actel proasic family of third-generation-architecture flash fpgas. versatiles are connected with any of the four levels of routing hierarchy. flas h switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programm ing. maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 v) programming of igloo plus devices via an ieee 1532 jtag interface. ? the aglp030 device does not support pll or sram.
igloo plus device family overview 1-4 revision 11 flash*freeze technology the igloo plus device has an ultra-low power stat ic mode, called flash*freeze mode, which retains all sram and register information and can still qu ickly return to normal operation. flash*freeze technology enables the user to quickly (within 1 s) enter and exit flash*freeze mode by activating the flash*freeze pin while all power supp lies are kept at their original va lues. in addition, i/os and global i/os can still be driven and can be toggling with out impact on power consum ption, clocks can still be driven or can be toggling without impact on power co nsumption, and the device retains all core registers, sram information, and i/o states. i/os can be individual ly configured to either hold their previous state or be tristated during flash*freeze mode. alternatively, they can be set to a certain state using weak pull- up or pull-down i/o attribute configuration. no power is consumed by the i/o banks, clocks, jtag pins, or pll, and the device consumes as little as 5 w in this mode. flash*freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. the flash*freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. refer to figure 1-2 for an illustration of entering/exiting flash*freeze mode. it is also possible to use the fl ash*freeze pin as a regular i/o if flash*freeze mode usage is not planned. * not supported by aglp030 devices figure 1-1 ? igloo plus device architecture overview with four i/o banks (aglp030, aglp060, and aglp125) ram block 4,608-bit dual-port sram or fifo block* versatile ccc i/os isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps bank 0 bank 1 bank 1 bank 3 bank 3 bank 2 * figure 1-2 ? igloo plus flash*freeze mode actel igloo plus fpga flash*freeze mode control flash*freeze pin
igloo plus low power flash fpgas revision 11 1-5 versatiles the igloo plus core consists of versatiles, which have been enhanced beyond the proasic plus ? core tiles. the igloo plus versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-3 for versatile configurations. user nonvolatile flashrom actel igloo plus devices have 1 kbit of on-ch ip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business models (for example, set-top boxes) ? secure key storage for secure communications algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using th e standard igloo plus ieee 1532 jtag programming interface. the core can be individually programmed (erased and written), and on-chip aes decryption can be used selectively to securely load data over public networ ks (except in aglp030 devices), as in security keys stored in the flashrom for a user design. the flashrom can be programmed via the jtag progr amming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. note that the flashrom can only be programmed from the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. a 7-bit address fr om the fpga core defines which of the 8 banks and which of the 16 bytes within that bank are being read. the three most significant bits (msbs) of the flashrom address determine the bank, and the four least significant bits (lsbs) of the flashrom address define the byte. the actel igloo plus development software solutions, libero ? integrated design environment (ide) and designer, have extensive support for the fl ashrom. one such featur e is auto-generation of sequential programming files for applications requir ing a unique serial number in each part. another feature allows the inclusion of st atic data for system version contro l. data for the flashrom can be generated quickly and easily using actel libero ide and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing flashrom contents. figure 1-3 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
igloo plus device family overview 1-6 revision 11 sram and fifo igloo plus devices (except aglp030 devices) ha ve embedded sram blocks along their north side. each variable-aspect-ratio sram block is 4,608 bits in size. available memory configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. the indi vidual blocks have independent read and write ports that can be configured with different bit widths on each port. for example, data can be sent through a 4-bit port and read as a single bitstream. the emb edded sram blocks can be initialized via the device jtag port (rom emulation mode) using the ujtag macro (except in aglp030 devices). in addition, every sram block has an embedded fi fo control unit. the contro l unit allows the sram block to be configured as a synchronous fifo with out using additional core versatiles. the fifo width and depth are programmable. the fi fo also features programmabl e almost empty (aempty) and almost full (afull) flags in addition to the norma l empty and full flags. the embedded fifo control unit contains the counters necessary for generati on of the read and write address pointers. the embedded sram/fifo blocks can be cascaded to create larger configurations. pll and ccc igloo plus devices provide designers with very fl exible clock conditioning circuit (ccc) capabilities. each member of the igloo plus family contains six cccs. one ccc (center west side) has a pll. the aglp030 device does not hav e a pll or cccs; it contains only inputs to six globals. the six ccc blocks are locate d at the four corners an d the centers of the east and west sides. one ccc (center west side) has a pll. the four corner cccs and the east ccc allow simple clock delay operations as well as clock spine access. the inputs of the six ccc blocks are accessible from the fpga core or from one of several inputs located near the ccc that have dedicated connections to the ccc block. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz up to 250 mhz ? output frequency range (f out_ccc ) = 0.75 mhz up to 250 mhz ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270. output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50% 1.5% or better (for pll only) ? low output jitter: worst case < 2.5% clock per iod peak-to-peak period jitter when single global network used (for pll only) ? maximum acquisition time is 300 s (for pll only) ? exceptional tolerance to input period jitter?allowabl e input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment between adjacent phases (for pll only) is 40 ps 250 mhz / f out_ccc global clocking igloo plus devices have extensive support for mu ltiple clocking domains. in addition to the ccc and pll support described above, there is a comp rehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the versanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.
igloo plus low power flash fpgas revision 11 1-7 i/os with advanced i/o standards the igloo plus family of fpgas features a flexible i/o structure, supporting a range of voltages (1.2 v, 1.5 v, 1.8 v, 2.5 v, 3.0 v wide range, and 3.3 v). igloo plus fpgas support many different i/o standards. the i/os are organized into four banks. all devices in igloo plus have four banks. the configuration of these banks determines the i/o standards supported. each i/o module contains several input , output, and output enable registers. hot-swap (also called hot-plug, or hot-insertion) is t he operation of hot-insertion or hot-removal of a card in a powered-up system. cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. wide range i/o support actel igloo plus devices support jedec-defined wide range i/o operation. igloo plus devices support both the jesd8-b sp ecification, covering 3 v and 3.3 v suppl ies, for an effective operating range of 2.7 v to 3.6 v, and jesd8-12 with its 1.2 v nominal , supporting an effective operating range of 1.14 v to 1.575 v. wider i/o range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components wit h greater tolerances. wide range eases i/o bank management and provides enhanc ed protection from system voltage sp ikes, while providing the flexibility to easily run custom voltage applications.

revision 11 2-1 2 ? igloo plus dc and switching characteristics general specifications operating conditions stresses beyond those listed in ta b l e 2 - 1 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the recommended o perating conditions specified in table 2-2 on page 2-2 is not implied. table 2-1 ? absolute maximum ratings symbol parameter limits units vcc dc core supply voltage ?0.3 to 1.65 v vjtag jtag dc voltage ?0.3 to 3.75 v vpump programming voltage ?0.3 to 3.75 v vccpll analog power supply (pll) ?0.3 to 1.65 v vcci dc i/o buffer supply voltage ?0.3 to 3.75 v vi 1 i/o input voltage ?0.3 v to 3.6 v v t stg 2 storage temperature ?65 to +150 c t j 2 junction temperature +125 c notes: 1. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 2-4 on page 2-3 . 2. for flash programming and retention maximum limits, refer to table 2-3 on page 2-2 , and for recommended operating limits, refer to table 2-2 on page 2-2 .
igloo plus dc and switching characteristics 2-2 revision 11 table 2-2 ? recommended operating conditions 1,2 symbol parameter commercial industrial units t a ambient temperature 0 to +70 ?40 to +85 c t j junction temperature 2 0 to + 85 ?40 to +100 c vcc 3 1.5 v dc core supply voltage 4 1.425 to 1.575 1.425 to 1.575 v 1.2 v?1.5 v wide range core voltage 5,6 1.14 to 1.575 1.14 to 1.575 v vjtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v vpump 7 programming voltage programming mo de 3.15 to 3.45 3.15 to 3.45 v operation 0 to 3.6 0 to 3.6 v vccpll 8 analog power supply (pll) 1.5 v dc core supply voltage 4 1.425 to 1.575 1.425 to 1.575 v 1.2 v?1.5 v wide range core voltage 5 1.14 to 1.575 1.14 to 1.575 v vcci 1.2 v dc supply voltage 5 1.14 to 1.26 1.14 to 1.26 v 1.2 v dc wide range supply voltage 5 1.14 to 1.575 1.14 to 1.575 v 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v wide range dc supply voltage 9 2.7 to 3.6 2.7 to 3.6 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v notes: 1. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 2. to ensure targeted reliability standards are met across ambient and junction operating temperatures, actel recommends that the user follow best design practices using actel?s timing and power simulation tools. 3. the ranges given here are for power supplies only. the recommended input voltage ranges specific to each i/o standard are given in table 2-21 on page 2-19 . vcci should be at the same voltage within a given i/o bank. 4. for igloo ? plus v5 devices 5. for igloo plus v2 devices only, operating at vcci vcc. 6. all igloo plus devices (v5 and v2) must be programmed wi th the vcc core voltage at 1.5 v. applications using v2 devices powered by a 1.2 v supply must switch th e core supply to 1.5 v for in-system programming. 7. vpump can be left floating during operation (not programming mode). 8. vccpll pins should be tied to vcc pins. see the pin descriptions chapter of the igloo plus fpga fabric user?s guide for further information. 9. 3.3 v wide range is compliant to the jdec8b specification and supports 3.0 v vcci operation. table 2-3 ? flash programming limits ? retention, storage, and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operating junction temperature t j (c) 2 commercial 500 20 years 110 100 industrial 500 20 years 110 100 notes: 1. this is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. these limits apply for program/data retention only. refer to table 2-1 on page 2-1 and table 2-2 for device operating conditions and absolute limits.
igloo plus low power flash fpgas revision 11 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is designed into every igloo plus device. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any sequ ence with minimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-4 . there are five regions to consider during power-up. igloo plus i/os are activated only if al l of the following three conditions are met: 1. vcc and vcci are above the mi nimum specified trip points ( figure 2-1 and figure 2-2 on page 2-5 ). 2. vcci > vcc ? 0.75 v (typical) 3. chip is in the operating mode. v cci trip point: ramping up (v5 devices): 0.6 v < trip_point_up < 1.2 v ramping down (v5 devices): 0.5 v < trip_point_down < 1.1 v ramping up (v2 devices): 0.75 v < trip_point_up < 1.05 v ramping down (v2 devices): 0.65 v < trip_point_down < 0.95 v v cc trip point: ramping up (v5 devices): 0.6 v < trip_point_up < 1.1 v ramping down (v5 devices): 0.5 v < trip_point_down < 1.0 v ramping up (v2 devices): 0.65 v < trip_point_up < 1.05 v ramping down (v2 devices): 0.55 v < trip_point_down < 0.95 v vcc and vcci ramp-up trip points are about 100 mv hi gher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tristated and weakly pulled up to vcci. ? jtag supply, pll power supplies, and charge pump vpump supply have no influence on i/o behavior. table 2-4 ? overshoot and undershoot limits 1 vcci average vcci?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of si x clock cycles. if the overshoot/unders hoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v.
igloo plus dc and switching characteristics 2-4 revision 11 pll behavior at brownout condition actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. power ramp-up should be monotonic at least until vcc and vccplx exceed brownout activation levels (see figure 2-1 and figure 2-2 on page 2-5 for more details). when pll power supply voltage and/or vcc levels drop below the vcc brownout levels (0.75 v 0.25 v for v5 devices, and 0.75 v 0.2 v for v2 devices), the pll output lock signal goes low and/or the output clock is lost. refer to the "brownout voltage" section in the "power-up/-down behavior of low power flash devices" chapter of the igloo plus device family user?s guide for information on clock and lock recovery. internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns delay from input buffer activation to make sure the transition from input buffers to output buffers is clean, en sure that there is no path longer than 100 ns from input buffer to output buffer in your design. figure 2-1 ? v5 devices ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because vcci / vcc are below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v vcc vcc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil, voh / vol, etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
igloo plus low power flash fpgas revision 11 2-5 figure 2-2 ? v2 devices ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because vcci/vcc are below specification. for the same reason, input buffers do not meet vih/vil levels, and output buffers do not meet voh/vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.14 v,1.425 v, 1.7 v, 2.3 v, or 3.0 v v cc vcc = 1.14 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.2 v deactivation trip point: v d = 0.75 v 0.2 v activation trip point: v a = 0.9 v 0.15 v deactivation trip point: v d = 0.8 v 0.15 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil , voh / vol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
igloo plus dc and switching characteristics 2-6 revision 11 thermal characteristics introduction the temperature variable in the actel designer soft ware refers to the junction temperature, not the ambient temperature. this is an important distin ction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. eq 1 can be used to calculate junction temperature. t j = junction temperature = t + t a eq 1 where: t a = ambient temperature t = temperature gradient between junction (silicon) and ambient t = ja * p ja = junction-to-ambient of the package. ja numbers are located in figure 2-5 . p = power dissipation package thermal characteristics the device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja . the thermal characteristics for ja are shown for two air flow rates. the maximum operating junction temperature is 100c. eq 2 shows a sample calculation of th e maximum operating power dissipation allowed for a 484-pin fbga package at commercial temperature and in still air. eq 2 temperature and voltage derating factors maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- ----------- 100 c70 c ? 20.5c/w ------------------------------------- 1.46 w = = = table 2-5 ? package thermal resistivities package type pin count jc ja units still air 200 ft./ min. 500 ft./ min. chip scale package (csp) 201 tbd tbd tbd tbd c/w 281 tbd tbd tbd tbd c/w 289 tbd tbd tbd tbd c/w very thin quad flat package (vqfp) 128 tbd tbd tbd tbd c/w 176 tbd tbd tbd tbd c/w table 2-6 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, v cc =1.425v) for igloo plus v2 or v5 devic es, 1.5 v dc core supply voltage array voltage vcc (v) junction temperature (c) ?40c 0c 25c 70c 85c 100c 1.425 0.934 0.953 0.971 1.000 1.007 1.013 1.5 0.855 0.874 0.891 0.917 0.924 0.929 1.575 0.799 0.816 0.832 0.857 0.864 0.868
igloo plus low power flash fpgas revision 11 2-7 calculating power dissipation quiescent supply current quiescent supply current (i dd ) calculation depends on multiple factors, including operating voltages (vcc, vcci, and vjtag), operati ng temperature, system clock frequency, and power mode usage. actel recommends using the power calculator and sm artpower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. table 2-7 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, v cc =1.14v) for igloo plus v2, 1.2 v dc core supply voltage array voltage vcc (v) junction temperature (c) ?40c 0c 25c 70c 85c 100c 1.14 0.963 0.975 0.989 1.000 1.007 1.011 1.2 0.853 0.865 .0877 0.893 0.893 0.897 1.26 0.781 0.792 0.803 0.813 0.819 0.822 table 2-8 ? power supply state per mode modes/power supplies power supply configurations vcc vccpll vcci vjtag vpump flash*freeze on on on on on/off/floating sleep off off on off off shutdown off off off off off no flash*freeze on on on on on/off/floating note: off: power supply level = 0 v table 2-9 ? quiescent supply current (idd) characteri stics, igloo plus flash*freeze mode* core voltage aglp030 aglp060 aglp125 units typical (25c) 1.2 v 4 8 13 a 1.5 v 6 10 18 a * i dd includes vcc, vpump, vcci, vjtag, and vccpll currents. table 2-10 ? quiescent supply current (idd) charac teristics, igloo plus sleep mode* icci current core voltage aglp030 aglp060 aglp125 units vcci = 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 a vcci = 1.5 v (per bank) typical (25c) 1.2 v / 1.5 v 1.8 1.8 1.8 a vcci = 1.8 v (per bank) typical (25c) 1.2 v / 1.5 v 1.9 1.9 1.9 a vcci = 2.5 v (per bank) typical (25c) 1.2 v / 1.5 v 2.2 2.2 2.2 a vcci = 3.3 v (per bank) typical (25c) 1.2 v / 1.5 v 2.5 2.5 2.5 a note: *idd = n banks * icci
igloo plus dc and switching characteristics 2-8 revision 11 table 2-11 ? quiescent supply current (idd) charac teristics, igloo pl us shutdown mode core voltage aglp030 aglp060 aglp125 units typical (25c) 1.2 v / 1.5 v 0 0 0 a table 2-12 ? quiescent supply current (idd), no igloo plus flash*freeze mode 1 core voltage aglp030 aglp060 aglp125 units icca current 2 typical (25c) 1.2 v 6 10 13 a 1.5 v 16 20 28 a icci or ijtag current vcci / vjtag = 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 a vcci / vjtag = 1.5 v (per bank) typical (25c) 1.2 v / 1.5 v 1.8 1.8 1.8 a vcci / vjtag = 1.8 v (per bank) typical (25c) 1.2 v / 1.5 v 1.9 1.9 1.9 a vcci / vjtag = 2.5 v (per bank) typical (25c) 1.2 v / 1.5 v 2.2 2.2 2.2 a vcci / vjtag = 3.3 v (per bank) typical (25c) 1.2 v / 1.5 v 2.5 2.5 2.5 a notes: 1. idd = n banks * icci + icca. jtag counts as one bank when powered. 2. includes vcc, vccpll, and vpump currents.
igloo plus low power flash fpgas revision 11 2-9 power per i/o pin table 2-13 ? summary of i/o input buffer power (per pin) ? default i/o software settings vcci (v) dynamic power pac9 (w/mhz) 1 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 16.26 3.3 v lvttl / 3.3 v lvcmos ? schmitt trigger 3.3 18.95 3.3 v lvcmos wide range 2 3.3 16.26 3.3 v lvcmos wide range 2 ? schmitt trigger 3.3 18.95 2.5 v lvcmos 2.5 4.59 2.5 v lvcmos ? schmitt trigger 2.5 6.01 1.8 v lvcmos 1.8 1.61 1.8 v lvcmos ? schmitt trigger 1.8 1.70 1.5 v lvcmos (jesd8-11) 1.5 0.96 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 0.90 1.2 v lvcmos 3 1.2 0.55 1.2 v lvcmos 3 ? schmitt trigger 1.2 0.47 1.2 v lvcmos wide range 3 1.2 0.55 1.2 v lvcmos wide range 3 ? schmitt trigger 1.2 0.47 notes: 1. pac9 is the total dynamic power measured on vcci. 2. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range as specified in the jesd-8b specification. 3. applicable for igloo plus v2 devices only, operating at vcci vcc. table 2-14 ? summary of i/o output bu ffer power (per pin) ? de fault i/o software settings 1 c load (pf) vcci (v) dynamic power pac10 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 5 3.3 127.11 3.3 v lvcmos wide range 3 5 3.3 127.11 2.5 v lvcmos 5 2.5 70.71 1.8 v lvcmos 5 1.8 35.57 1.5 v lvcmos (jesd8-11) 5 1.5 24.30 1.2 v lvcmos 4 51.2 15.22 1.2 v lvcmos wide range 4 51.2 15.22 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. pac10 is the total dynamic power measured on vcci. 3. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range as specified in the jesd-8b specification. 4. applicable for igloo plus v2 devices only, operating at vcci vcc.
igloo plus dc and switching characteristics 2-10 revision 11 power consumption of vari ous internal resources table 2-15 ? different components contribu ting to dynamic power consumption in igloo plus devices for igloo plus v2 or v5 devi ces, 1.5 v core supply voltage parameter definition device specific dynamic power (w/mhz) aglp125 aglp060 aglp030 pac1 clock contribution of a global rib 11.03 9.3 9.3 pac2 clock contribution of a global spine 0.81 0.81 0.41 pac3 clock contribution of a versatile row 0.81 pac4 clock contribution of a versat ile used as a sequential module 0.11 pac5 first contribution of a versatile used as a sequential module 0.057 pac6 second contribution of a versatil e used as a sequential module 0.207 pac7 contribution of a versatile us ed as a combinatorial module 0.17 pac8 average contribution of a routing net 0.7 pac9 contribution of an i/o input pin (standard-dependent) see table 2-13 on page 2-9 . pac10 contribution of an i/o out put pin (standard-dependent) see table 2-14 on page 2-9 . pac11 average contribution of a ram block during a read operation 25.00 pac12 average contribution of a ram block during a write operation 30.00 pac13 dynamic contribution for pll 2.70
igloo plus low power flash fpgas revision 11 2-11 table 2-16 ? different components contributing to the static power consumption in igloo plus devices for igloo plus v2 or v5 devices, 1.5 v core supply voltage parameter definition device-specific static power (mw) aglp125 aglp060 aglp030 pdc1 array static power in active mode see table 2-12 on page 2-8 pdc2 array static power in static (idle) mode see table 2-11 on page 2-8 pdc3 array static power in flash*freeze mode see table 2-9 on page 2-7 pdc4 static pll contribution 1.84 1 pdc5 bank quiescent power (vcci-dependent) see table 2-12 on page 2-8 notes: 1. this is the minimum contribution of the pll when operating at lowest frequency. 2. for a different output load, drive strength, or slew rate, actel recommends using the actel power spreadsheet calculator or the smartpower tool in actel libero ? integrated design environment (ide) software. table 2-17 ? different components contribu ting to dynamic power consumption in igloo plus devices for igloo plus v2 devices, 1.2 v core supply voltage parameter definition device-specific dynamic power (w/mhz) aglp125 aglp060 aglp030 pac1 clock contribution of a global rib 7.07 5.96 5.96 pac2 clock contribution of a global spine 0.52 0.52 0.26 pac3 clock contribution of a versatile row 0.52 pac4 clock contribution of a versatile used as a sequential module 0.07 pac5 first contribution of a versatile used as a sequential module 0.045 pac6 second contribution of a versatil e used as a sequential module 0.186 pac7 contribution of a versatile us ed as a combinatorial module 0.11 pac8 average contribution of a routing net 0.45 pac9 contribution of an i/o in put pin (standard-dependent) see table 2-13 on page 2-9 pac10 contribution of an i/o output pin (standard-dependent) see table 2-14 on page 2-9 pac11 average contribution of a ram block during a read operation 25.00 pac12 average contribution of a ram block during a write operation 30.00 pac13 dynamic contribution for pll 2.10
igloo plus dc and switching characteristics 2-12 revision 11 power calculation methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in actel libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number a nd the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-19 on page 2-14 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-20 on page 2-14 . ? read rate and write rate to the memory?guidel ines are provided for typical applications in table 2-20 on page 2-14 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = (p dc1 or p dc2 or p dc3 ) + n banks * p dc5 n banks is the number of i/o banks powered in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (p ac1 + n spine *p ac2 + n row *p ac3 + n s-cell * p ac4 ) * f clk n spine is the number of global spines used in the user design?guidelines are provided in table 2-19 on page 2-14 . n row is the number of versatile rows used in the design?guidelines are provided in table 2-19 on page 2-14 . table 2-18 ? different components contributing to the static power consumption in igloo plus devices for igloo plus v2 devices, 1.2 v core supply voltage parameter definition device-specific static power (mw) aglp125 aglp060 aglp030 pdc1 array static power in active mode see table 2-12 on page 2-8 pdc2 array static power in static (idle) mode see table 2-11 on page 2-8 pdc3 array static power in flash*freeze mode see table 2-9 on page 2-7 pdc4 static pll contribution 0.90 1 pdc5 bank quiescent power (vcci-dependent) see table 2-12 on page 2-8 notes: 1. this is the minimum contribution of the pll when operating at lowest frequency. 2. for a different output load, drive strength, or slew rate, actel recommends using the actel power spreadsheet calculator or the smartpower tool in actel libero ide software.
igloo plus low power flash fpgas revision 11 2-13 f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. p ac1 , p ac2 , p ac3 , and p ac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (p ac5 + 1 / 2 * p ac6 ) * f clk n s-cell is the number of versatiles used as sequential modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. combinatorial cells contribution?p c-cell p c-cell = n c-cell * 1 / 2 * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * 1 / 2 * p ac8 * f clk n s-cell is the number of versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * 2 / 2 * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * 2 / 2 * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-19 on page 2-14 . 1 is the i/o buffer enable rate?guidelines are provided in table 2-20 on page 2-14 . f clk is the global clock signal frequency. ram contribution?p memory p memory = p ac11 * n blocks * f read-clock * 2 + p ac12 * n block * f write-clock * 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. 3 is the ram enable rate for write operations?guidelines are provided in table 2-20 on page 2-14 . pll contribution?p pll p pll = p dc4 + p ac13 *f clkout f clkout is the output clock frequency. 1
igloo plus dc and switching characteristics 2-14 revision 11 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when nontristate output buffers are used, the enable rate should be 100%. 1. if a pll is used to generate more than one output clock, incl ude each output clock in the formula by adding its corresponding contribution (p ac13 * f clkout product) to the total pll contribution. table 2-19 ? toggle rate guidelines reco mmended for power calculation component definition guideline 1 toggle rate of versatile outputs 10% 2 i/o buffer toggle rate 10% table 2-20 ? enable rate guidelines recomme nded for power calculation component definition guideline 1 i/o output buffer enable rate 100% 2 ram enable rate for read operations 12.5% 3 ram enable rate for write operations 12.5%
igloo plus low power flash fpgas revision 11 2-15 user i/o characteristics timing model figure 2-3 ? timing model operating conditions: std speed, commercial temperature range (t j = 70c), worst-case v cc = 1.425 v, for dc 1.5 v core voltage, applicable to v2 and v5 devices dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvcmos 2.5 v output drive strength = 12 ma high slew rate input lvcmos 2.5 v lvcmos 1.5 v lvttl 3.3 v output drive strength = 12 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 1.40 ns t pd = 0.89 ns t dp = 1.62 ns t pd = 1.98 ns t dp = 1.62 ns t pd = 1.24 ns t dp = 1.70 ns t pd = 0.86 ns t dp = 2.07 ns t pd = 0.87 ns t py = 0.85 ns t clkq = 0.80 ns t oclkq = 0.89 ns t sud = 0.84 ns t osud = 0.18 ns t dp = 1.62 ns t py = 0.85 ns t py = 1.15 ns t clkq = 0.80 ns t sud = 0.84 ns t py = 0.85 ns t iclkq = 0.63 ns t isud = 0.18 ns t py = 1.06 ns
igloo plus dc and switching characteristics 2-16 revision 11 figure 2-4 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50% 50% vih vcc vil t dout (r) din gnd t dout (f) 50% 50% vcc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
igloo plus low power flash fpgas revision 11 2-17 figure 2-5 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) vtrip vtrip voh vcc d 50% 50% vcc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
igloo plus dc and switching characteristics 2-18 revision 11 figure 2-6 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci t zl vtrip 50% t hz 90% vcci t zh vtrip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls vtrip 50% t zhs vtrip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% vcc vcc vcc vcci vcc vcc vcc voh vol vol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
igloo plus low power flash fpgas revision 11 2-19 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-21 ? summary of maximum and minimum dc input and ou tput levels applicable to commercial and industrial conditions?s oftware default settings i/o standard drive strength equiv. software default drive strength option 2 slew rate vil vih vol voh i ol 1 i oh 1 min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 v lvcmos wide range 3 100 a 12 ma high ?0.3 0.8 2 3.6 0.2 vdd 3 0.2 0.1 0.1 2.5 v lvcmos 12 ma 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 8 ma 8 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0. 45 vcci ? 0.45 8 8 1.5 v lvcmos 4 ma 4 ma high ?0.3 0.35 * v cci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 4 4 1.2 v lvcmos 4 2 ma 2 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 1.2 v lvcmos wide range 4,5 100 a 2 ma high ?0.3 0.3 * vcci 0.7 * vcci 3.6 0.1 vcci ? 0.1 0.1 0.1 notes: 1. currents are measured at 85c junction temperature. 2. note that 1.2 v lvcmos and 3.3 v lvcmos wide range are applicable to 100 a drive strength only. the configuration will not operate at the equivalent software default driv e strength. these values are for normal ranges only. 3. all lvcmos 3.3 v software macros support lvcmos 3. 3 v wide range as specified in the jesd-8b specification. 4. applicable to igloo plus v2 devices operating at v cci v cc . 5. all lvcmos 1.2 v software macros support lvcmos 1. 2 v wide range as specified in the jesd8-12 specification.
igloo plus dc and switching characteristics 2-20 revision 11 table 2-22 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions dc i/o standards commercial 1 industrial 2 iil 3 iih 4 iil 3 iih 4 a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 3.3 v lvcmos wide range 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 1.2 v lvcmos 5 10 10 15 15 1.2 v lvcmos wide range 5 10 10 15 15 notes: 1. commercial range (0c < t a < 70c) 2. industrial range (?40c < t a < 85c) 3. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 4. iih is the input leakage current per i/o pin over reco mmended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 5. applicable to igloo plus v2 devices operating at v cci v cc .
igloo plus low power flash fpgas revision 11 2-21 summary of i/o timing characteristi cs ? default i/o software settings table 2-23 ? summary of ac measuring points standard measuring trip point (vtrip) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 3.3 v lvcmos wide range 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 1.2 v lvcmos 0.60 v 1.2 v lvcmos wide range 0.60 v table 2-24 ? i/o ac parameter definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer delay through the i/o interface t eout enable to output buffer tristate control delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
igloo plus dc and switching characteristics 2-22 revision 11 table 2-25 ? summary of i/o timing characteristics?so ftware default settings, std speed grade, commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v i/o standard drive strength equivalent software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ) t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 pf ? 0.97 1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 ns 3.3 v lvcmos wide range 2 100 a 12 ma high 5 pf ? 0.97 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 ns 2.5 v lvcmos 12 ma 12 ma high 5 pf ? 0.97 1.77 0.18 1.06 1.22 0.66 1.81 1.51 2.22 2.56 ns 1.8 v lvcmos 8 ma 8 ma high 5 pf ? 0.97 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 ns 1.5 v lvcmos 4 ma 4 ma high 5 pf ? 0.97 2.29 0.18 1.16 1.62 0.66 2.33 2.00 2.37 2.57 ns notes: 1. note that 3.3 v lvcmos wide range is applicable to 100 a dr ive strength only. the configuration will not operate at the equivalent software default drive strength. these values are for normal ranges only. 2. all lvcmos 3.3 v software macros support lvcmos 3. 3 v wide range as specified in the jesd-8b specification. 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus low power flash fpgas revision 11 2-23 table 2-26 ? summary of i/o timing characteristics?so ftware default setting s, std speed grade commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v i/o standard drive strength equivalent software default drive strength option 1 slew rate capacitive load (pf) external resistor ( ) t dout t dp t din t py ) t pys t eout t zl t zh t lz t hz units 3.3 v lvttl / 3.3 v lvcmos 12 ma 12 ma high 5 pf ? 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns 3.3 v lvcmos wide range 2 100 a 12 ma high 5 pf ? 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns 2.5 v lvcmos 12 ma 12 ma high 5 pf ? 0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27 ns 1.8 v lvcmos 8 ma 8 ma high 5 pf ? 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns 1.5 v lvcmos 4 ma 4 ma high 5 pf ? 0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15 ns 1.2 v lvcmos 2 ma 2 ma high 5 pf ? 0.98 3 .380.191.572.340.673.262.782.993.24ns 1.2 v lvcmos wide range 3 100 a 2 ma high 5 pf ? 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros support lvcmos 3. 3 v wide range as specified in the jesd-8b specification. 3. all lvcmos 1.2 v software macros support lvcmos 1. 2 v wide range as specified in the jesd8-12 specification. 4. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-24 revision 11 detailed i/o dc characteristics table 2-27 ? input capacitance symbol definition conditions min. max. units c in input capacitance vin = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin vin = 0, f = 1.0 mhz 8 pf table 2-28 ? i/o output buffer maximum resistances 1 standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 25 75 3.3 v lvcmos wide range 100 a same as equivalent software default drive 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 1.2 v lvcmos 2 ma 157.5 163.8 1.2 v lvcmos wide range 4 100 a 157.5 163.8 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis model on the actel website at http://www.actel.com/dow nload/ibis/default.aspx . 2. r (pull-down-max) = (volspec) / i olspec 3. r (pull-up-max) = (vccimax ? vohspec) / i ohspec 4. applicable to igloo plus v2 devices operating at vcci vcc.
igloo plus low power flash fpgas revision 11 2-25 table 2-29 ? i/o weak pull-up/pull-down resistances minimum and maximum weak pull-u p/pull-down resistance values vcci r (weak pull-up) 1 ( ) r (weak pull-down) 2 ( ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 3.3 v (wide range i/os) 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k 1.2 v 25 k 110 k 25 k 150 k 1.2 v (wide range i/os) 19 k 110 k 19 k 150 k notes: 1. r (weak pull-up-max) = (vccimax ? vohspec) / i (weak pull-up-min) 2. r (weak pulldown-max) = (volspec) / i (weak pulldown-min) table 2-30 ? i/o short currents i osh /i osl drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 109 103 3.3 v lvcmos wide range 100 a same as equivalent software default drive 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 12 ma 74 65 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 44 35 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 1.2 v lvcmos 2 ma 26 20 1.2 v lvcmos wide range 100 a 26 20 * t j = 100c
igloo plus dc and switching characteristics 2-26 revision 11 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, which is the worst case for this type of analysis. for example, at 100c, the short current condition would have to be sustained for more than six months to cause a reliability concern. the i/o design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-31 ? duration of short circ uit event before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months table 2-32 ? schmitt trigger input hysteresis hysteresis voltage value (typ.) for schmitt mode input buffers input buffer conf iguration hysteresis value (typ.) 3.3 v lvttl/lvcmos (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmitt trigger mode) 80 mv 1.5 v lvcmos (schmitt trigger mode) 60 mv 1.2 v lvcmos (schmitt trigger mode) 40 mv table 2-33 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos (schmitt trigger disabled) no requirement 10 ns * 20 years (100c) lvttl/lvcmos (schmitt trigger enabled) no requirement no requirement, but input noise voltage cannot exceed schmitt hysteresis. 20 years (100c) * the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, then the rise time and fall time of input bu ffers can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
igloo plus low power flash fpgas revision 11 2-27 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-34 ? minimum and maximum dc input and output levels 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh i ol i oh i osl i osh i il 1 i ih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-35 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.45 * measuring point = vtrip. see table 2-23 on page 2-21 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo plus dc and switching characteristics 2-28 revision 11 timing characteristics applies to 1.5 v dc core voltage applies to 1.2 v dc core voltage table 2-36 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 3.94 0.18 0.85 1.15 0.66 4.02 3.46 1.82 1.87 ns 6 ma std 0.97 3.20 0.18 0.85 1.15 0.66 3.27 2.94 2.04 2.27 ns 8 ma std 0.97 3.20 0.18 0.85 1.15 0.66 3.27 2.94 2.04 2.27 ns 12 ma std 0.97 2.72 0.18 0.85 1.15 0.66 2.78 2.57 2.20 2.53 ns 16 ma std 0.97 2.72 0.18 0.85 1.15 0.66 2.78 2.57 2.20 2.53 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-37 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 2.36 0.18 0.85 1.15 0.66 2.41 1.90 1.82 1.98 ns 6 ma std 0.97 1.96 0.18 0.85 1.15 0.66 2.01 1.56 2.04 2.38 ns 8 ma std 0.97 1.96 0.18 0.85 1.15 0.66 2.01 1.56 2.04 2.38 ns 12 ma std 0.97 1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 ns 16 ma std 0.97 1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray. table 2-38 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 4.56 0.19 0.99 1.37 0.67 4.63 3.98 2.26 2.57 ns 6 ma std 0.98 3.80 0.19 0.99 1.37 0.67 3.96 3.45 2.49 2.98 ns 8 ma std 0.98 3.80 0.19 0.99 137 0.67 3.86 3.45 2.49 2.98 ns 12 ma std 0.98 3.31 0.19 0.99 1.37 0.67 3.36 3.07 2.65 3.25 ns 16 ma std 0.98 3.31 0.19 0.99 1.37 0.67 3.36 3.07 2.65 3.25 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-39 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 2.92 0.19 0.99 1.37 0.67 2.97 2.38 2.25 2.70 ns 6 ma std 0.98 2.52 0.19 0.99 1.37 0.67 2.56 2.03 2.49 3.11 ns 8 ma std 0.98 2.52 0.19 0.99 1.37 0.67 2.56 2.03 2.49 3.11 ns 12 ma std 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns 16 ma std 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray
igloo plus low power flash fpgas revision 11 2-29 3.3 v lvcmos wide range table 2-40 ? minimum and maximum dc input and output levels 3.3 v lvcmos wide range equivalent software default drive strength option 1 vil vih vol voh i ol i oh i osl i osh i il 2 i ih 3 drive strength min. v max. v min. v max. v max. v min. vaa max. a 4 max. a 4 a 5 a 5 100 a 2 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 25 27 10 10 100 a 4 ma ?0.3 0.8 2 3.6 0.4 vdd ? 0.2 100 100 25 27 10 10 100 a 6 ma ?0.3 0.8 2 3.6 0.4 vdd ? 0.2 100 100 51 54 10 10 100 a 8 ma ?0.3 0.8 2 3.6 0.4 vdd ? 0.2 100 100 51 54 10 10 100 a 12 ma ?0.3 0.8 2 3.6 0.4 vdd ? 0.2 100 100 103 109 10 10 100 a 16 ma ?0.3 0.8 2 3.6 0.4 vdd ? 0.2 100 100 103 109 10 10 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 3. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < v cci. input current is larger when operating outside recommended ranges. 4. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 5. currents are measured at 85c junction temperature. 6. software default selection highlighted in gray. table 2-41 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.45 * measuring point = vtrip. see table 2-23 on page 2-21 for a complete table of trip points.
igloo plus dc and switching characteristics 2-30 revision 11 timing characteristics applies to 1.5 v dc core voltage applies to 1.2 v dc core voltage table 2-42 ? 3.3 v lvcmos wide range low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 4 ma std 0.97 5.85 0.18 1.18 1.64 0.66 5.86 5.05 2.57 2.57 ns 100 a 6 ma std 0.97 4.70 0.18 1.18 1.64 0.66 4.72 4.27 2.92 3.19 ns 100 a 8 ma std 0.97 4.70 0.18 1.18 1.64 0.66 4.72 4.27 2.92 3.19 ns 100 a 12 ma std 0.97 3.96 0.18 1.1 8 1.64 0.66 3.98 3.70 3.16 3.59 ns 100 a 16 ma std 0.97 3.96 0.18 1.1 8 1.64 0.66 3.98 3.70 3.16 3.59 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-43 ? 3.3 v lvcmos wide range high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 4 ma std 0.97 3.39 0.18 1.18 1.64 0.66 3.41 2.69 2.57 2.73 ns 100 a 6 ma std 0.97 2.79 0.18 1.18 1.64 0.66 2.80 2.17 2.92 3.36 ns 100 a 8 ma std 0.97 2.79 0.18 1.18 1.64 0.66 2.80 2.17 2.92 3.36 ns 100 a 12 ma std 0.97 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 ns 100 a 16 ma std 0.97 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 3. software default selection highlighted in gray.
igloo plus low power flash fpgas revision 11 2-31 table 2-44 ? 3.3 v lvcmos wide range low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 4 ma std 0.98 6.68 0.19 1.32 1.92 0.67 6.68 5.74 3.13 3.47 ns 100 a 6 ma std 0.98 5.51 0.19 1.32 1.92 0.67 5.51 4.94 3.48 4.11 ns 100 a 8 ma std 0.98 5.51 0.19 1.32 1.92 0.67 5.51 4.94 3.48 4.11 ns 100 a 12 ma std 0.98 4.75 0.19 1.32 1.92 0.67 4.75 4.36 3.73 4.52 ns 100 a 16 ma std 0.98 4.75 0.19 1.32 1.92 0.67 4.75 4.36 3.73 4.52 ns notes: 1. the minimum drive strength for any lv cmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-45 ? 3.3 v lvcmos wide range high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 4 ma std 0.98 4.16 0.19 1.32 1.92 0.67 4.16 3.32 3.12 3.66 ns 100 a 6 ma std 0.98 3.54 0.19 1.32 1.92 0.67 3.54 2.79 3.48 4.31 ns 100 a 8 ma std 0.98 3.54 0.19 1.32 1.92 0.67 3.54 2.79 3.48 4.31 ns 100 a 12 ma std 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns 100 a 16 ma std 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 3. software default selection highlighted in gray.
igloo plus dc and switching characteristics 2-32 revision 11 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. table 2-46 ? minimum and maximum dc input and output levels 2.5 v lvcmos vil vih vol voh i ol i oh i osl i osh i il 1 i ih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 65 74 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-47 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.25 * measuring point = vtrip. see table 2-23 on page 2-21 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo plus low power flash fpgas revision 11 2-33 timing characteristics applies to 1.5 v dc core voltage applies to 1.2 v dc core voltage table 2-48 ? 2.5 v lvcmos low slew ? appli es to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 4.44 0.18 1.06 1.22 0.66 4.53 4.15 1.80 1.70 ns 6 ma std 0.97 3.61 0.18 1.06 1.22 0.66 3.69 3.50 2.05 2.18 ns 8 ma std 0.97 3.61 0.18 1.06 1.22 0.66 3.69 3.50 2.05 2.18 ns 12 ma std 0.97 3.07 0.18 1.06 1.22 0.66 3.14 3.03 2.22 2.48 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-49 ? 2.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 2.41 0.18 1.06 1.22 0.66 2.47 2.22 1.79 1.77 ns 6 ma std 0.97 1.99 0.18 1.06 1.22 0.66 2.04 1.75 2.04 2.25 ns 8 ma std 0.97 1.99 0.18 1.06 1.22 0.66 2.04 1.75 2.04 2.25 ns 12 ma std 0.97 1.77 0.18 1.06 1.22 0.66 1.81 1.51 2.22 2.56 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray. table 2-50 ? 2.5 lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 5.04 0.19 1.19 1.40 0.67 5.12 4.65 2.22 2.36 ns 6 ma std 0.98 4.19 0.19 1.19 1.40 0.67 4.25 3.98 2.48 2.85 ns 8 ma std 0.98 4.19 0.19 1.19 1.40 0.67 4.25 3.98 2.48 2.85 ns 12 ma std 0.98 3.63 0.19 1.19 1.40 0.67 3.69 3.50 2.66 3.16 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-51 ? 2.5 v lvcmos high slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 2.96 0.19 1.19 1.40 0.67 3.00 2.67 2.22 2.46 ns 6 ma std 0.98 2.52 0.19 1.19 1.40 0.67 2.56 2.18 2.47 2.95 ns 8 ma std 0.98 2.52 0.19 1.19 1.40 0.67 2.56 2.18 2.47 2.95 ns 12 ma std 0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray.
igloo plus dc and switching characteristics 2-34 revision 11 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standa rd (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-52 ? minimum and maximum dc input and output levels 1.8 v lvcmos vil vih vol voh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3. 6 0.45 vcci ? 0.45 4 4 17 22 10 10 6 ma ?0.3 0.35 * vcci 0.65 * v cci 3.6 0.45 vcci ? 0.45 6 6 35 44 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 8 8 35 44 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-53 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.95 * measuring point = vtrip. see table 2-23 on page 2-21 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo plus low power flash fpgas revision 11 2-35 timing characteristics applies to 1.5 v dc core voltage applies to 1.2 v dc core voltage table 2-54 ? 1.8 v lvcmos low slew ? appli es to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 5.89 0.18 1.00 1.43 0.66 6.01 5.43 1.78 1.30 ns 4 ma std 0.97 4.82 0.18 1.00 1.43 0.66 4.92 4.56 2.08 2.08 ns 6 ma std 0.97 4.13 0.18 1.00 1.43 0.66 4.21 3.96 2.30 2.46 ns 8 ma std 0.97 4.13 0.18 1.00 1.43 0.66 4.21 3.96 2.30 2.46 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-55 ? 1.8 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.82 0.18 1.00 1.43 0.66 2.88 2.78 1.78 1.35 ns 4 ma std 0.97 2.30 0.18 1.00 1.43 0.66 2.35 2.11 2.08 2.15 ns 6 ma std 0.97 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 ns 8 ma std 0.97 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray. table 2-56 ? 1.8 v lvcmos low slew ? appli es to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 6.43 0.19 1.12 1.61 0.67 6.54 5.93 2.19 1.88 ns 4 ma std 0.98 5.33 0.19 1.12 1.61 0.67 5.41 5.03 2.50 2.68 ns 6 ma std 0.98 4.61 0.19 1.12 1.61 0.67 4.69 4.41 2.72 3.07 ns 8 ma std 0.98 4.61 0.19 1.12 1.61 0.67 4.69 4.41 2.72 3.07 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-57 ? 1.8 v lvcmos high slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 3.30 0.19 1.12 1.61 0.67 3.34 3.21 2.19 1.93 ns 4 ma std 0.98 2.76 0.19 1.12 1.61 0.67 2.79 2.51 2.50 2.76 ns 6 ma std 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns 8 ma std 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray.
igloo plus dc and switching characteristics 2-36 revision 11 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-58 ? minimum and maximum dc input and output levels 1.5 v lvcmos vil vih vol voh i ol i oh i osl i osh i il 1 i ih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.35 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 13 16 10 10 4 ma ?0.3 0.35 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 4 4 25 33 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-10 ? ac loading table 2-59 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.50.755 * measuring point = vtrip. see table 2-23 on page 2-21 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo plus low power flash fpgas revision 11 2-37 timing characteristics applies to 1.5 v dc core voltage applies to 1.2 v dc core voltage table 2-60 ? 1.5 v lvcmos low slew ? appli es to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 6.07 0.18 1.16 1.62 0.66 6.19 5.53 2.13 2.02 ns 4 ma std 0.97 5.24 0.18 1.16 1.62 0.66 5.34 4.81 2.37 2.47 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-61 ? 1.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.65 0.18 1.16 1.62 0.66 2.71 2.43 2.13 2.11 ns 4 ma std 0.97 2.29 0.18 1.16 1.62 0.66 2.33 2.00 2.37 2.57 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray. table 2-62 ? 1.5 v lvcmos low slew ? appli es to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 6.57 0.19 1.26 1.80 0.67 6.68 6.01 2.54 2.59 ns 4 ma std 0.98 5.72 0.19 1.26 1.80 0.67 5.81 5.27 2.79 3.05 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-63 ? 1.5 v lvcmos high slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 3.08 0.19 1.26 1.80 0.67 3.13 2.82 2.53 2.68 ns 4 ma std 0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray.
igloo plus dc and switching characteristics 2-38 revision 11 1.2 v lvcmos (jesd8-12a) low-voltage cmos for 1.2 v complies with the lvcm os standard jesd8-12a for general purpose 1.2 v applications. it uses a 1.2 v input buffer and a push-pull output buffer. timing characteristics applies to 1.2 v dc core voltage table 2-64 ? minimum and maximum dc input and output levels 1.2 v lvcmos 1 v il v ih v ol v oh i ol i oh i osl i osh i il 2 i ih 3 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 4 max. ma 4 a 5 a 5 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 20 26 10 10 notes: 1. applicable to igloo nano v2 devices operating at vcci vcc. 2. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 3. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 4. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 5. currents are measured at 85c junction temperature. 6. software default selection highlighted in gray. figure 2-11 ? ac loading table 2-65 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.20.65 * measuring point = vtrip. see table 2-23 on page 2-21 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz table 2-66 ? 1.2 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 8.27 0.19 1.57 2.34 0.67 7.94 6.77 3.00 3.11 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-67 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. software default selection highlighted in gray.
igloo plus low power flash fpgas revision 11 2-39 1.2 v lvcmos wide range table 2-68 ? minimum and maximum dc input and output levels 1.2 v lvcmos wide range 1 v il v ih v ol v oh i ol i oh i osl i osh i il 3 i ih 4 drive strength equivalent software default drive strength option 2 min. v max. v min. v max. v max. v min. vmama max. ma 5 max ma 5 a 6 a 6 100 a 2ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 20 26 10 10 notes: 1. applicable to v2 devices only. 2. the minimum drive strength for any lvcmos 1.2 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 3. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 4. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 5. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 6. currents are measured at 85c junction temperature. 7. software default selection highlighted in gray. table 2-69 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.20.65 * measuring point = vtrip. see table 2-23 on page 2-21 for a complete table of trip points.
igloo plus dc and switching characteristics 2-40 revision 11 timing characteristics applies to 1.2 v dc core voltage table 2-70 ? 1.2 v lvcmos wide range low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std 0.98 8.27 0.19 1.57 2.34 0.67 7.94 6.77 3.00 3.11 ns notes: 1. the minimum drive strength for any lv cmos 1.2 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-71 ? 1.2 v lvcmos wide range high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case vcci = 1.14 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 3. software default selection highlighted in gray.
igloo plus low power flash fpgas revision 11 2-41 i/o register specifications fully registered i/o buffers with asynchronous preset figure 2-12 ? timing model of registered i/o buffers with asynchronous preset inbuf inbuf tribuf clkbuf inbuf clkbuf data input i/o register with: active high preset positive-edge triggered data output register and enable output register with: active high preset postive-edge triggered pad out clk preset data_out data eout dout clk dq dfn1p1 pre dq dfn1p1 pre dq dfn1p1 pre d_enable a c d e f h i j l y core array
igloo plus dc and switching characteristics 2-42 revision 11 table 2-72 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t opre2q asynchronous preset-to-q of the output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the output enable register j, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time for the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t ipre2q asynchronous preset-to-q of th e input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a * see figure 2-12 on page 2-41 for more information.
igloo plus low power flash fpgas revision 11 2-43 fully registered i/o buff ers with asynchronous clear figure 2-13 ? timing model of the registered i/o buffers with asynchronous clear clk pad out clk clr data_out data y aa eout dout core array dq dfn1c1 clr dq dfn1c1 clr dq dfn1c1 clr d_enable cc dd ee ff ll hh jj clkbuf inbuf tribuf inbuf clkbuf inbuf data input i/o register with active high clear positive-edge triggered data output register and enable output register with active high clear positive-edge triggered
igloo plus dc and switching characteristics 2-44 revision 11 table 2-73 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa * see figure 2-13 on page 2-43 for more information.
igloo plus low power flash fpgas revision 11 2-45 input register timing characteristics 1.5 v dc core voltage figure 2-14 ? input register timing diagram 50% clear out_1 clk data preset 50% t isud t ihd 50% 50% t iclkq 1 0 t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-74 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t iclkq clock-to-q of the input data register 0.41 ns t isud data setup time for the input data register 0.32 ns t ihd data hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.57 ns t ipre2q asynchronous preset-to-q of th e input data register 0.57 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.24 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.24 ns t iwclr asynchronous clear minimum pulse widt h for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse widt h for the input data register 0.19 ns t ickmpwh clock minimum pulse width high for the input data register 0.31 ns t ickmpwl clock minimum pulse width low for the input data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-46 revision 11 1.2 v dc core voltage table 2-75 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t iclkq clock-to-q of the input data register 0.66 ns t isud data setup time for the input data register 0.43 ns t ihd data hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.86 ns t ipre2q asynchronous preset-to-q of th e input data register 0.86 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.24 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.24 ns t iwclr asynchronous clear minimum pulse widt h for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse widt h for the input data register 0.19 ns t ickmpwh clock minimum pulse width high for the input data register 0.31 ns t ickmpwl clock minimum pulse width low for the input data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus low power flash fpgas revision 11 2-47 output register timing characteristics 1.5 v dc core voltage figure 2-15 ? output register timing diagram clear dout clk data_out preset 50% t osud t ohd 50% 50% t oclkq 1 0 t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-76 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t oclkq clock-to-q of the output data register 0.66 ns t osud data setup time for the ou tput data register 0.33 ns t ohd data hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 0.82 ns t opre2q asynchronous preset-to-q of t he output data register 0.88 ns t oremclr asynchronous clear removal time fo r the output data register 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.24 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.24 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 ns t owpre asynchronous preset minimum pulse widt h for the output data register 0.19 ns t ockmpwh clock minimum pulse width high for the output data register 0.31 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-48 revision 11 1.2 v dc core voltage table 2-77 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t oclkq clock-to-q of the output data register 1.03 ns t osud data setup time for the ou tput data register 0.52 ns t ohd data hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 1.22 ns t opre2q asynchronous preset-to-q of t he output data register 1.31 ns t oremclr asynchronous clear removal time fo r the output data register 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.24 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.24 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 ns t owpre asynchronous preset minimum pulse widt h for the output data register 0.19 ns t ockmpwh clock minimum pulse width high for the output data register 0.31 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus low power flash fpgas revision 11 2-49 output enable register timing characteristics 1.5 v dc core voltage figure 2-16 ? output enable register timing diagram 50% preset clear eout clk d_enable 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-78 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t oeclkq clock-to-q of the output enable register 0.68 ns t oesud data setup time for the output enable register 0.33 ns t oehd data hold time for the output enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 0.84 ns t oepre2q asynchronous preset-to-q of the output enable register 0.91 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.24 ns t oerempre asynchronous preset removal time for the output enable register 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.24 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-50 revision 11 1.2 v dc core voltage table 2-79 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t oeclkq clock-to-q of the output enable register 1.06 ns t oesud data setup time for the output enable register 0.52 ns t oehd data hold time for the output enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 1.25 ns t oepre2q asynchronous preset-to-q of the output enable register 1.36 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.24 ns t oerempre asynchronous preset removal time for the output enable register 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.24 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus low power flash fpgas revision 11 2-51 versatile characteristics versatile specifications as a combinatorial module the igloo plus library offers all co mbinations of lut-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the fusion, igloo/e, and proasic3/ e macro library guide . figure 2-17 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
igloo plus dc and switching characteristics 2-52 revision 11 figure 2-18 ? timing model and waveforms net a y b length = 1 versatile net a y b length = 1 versatile net a y b length = 1 versatile net a y b length = 1 versatile nand2 or any combinatorial logic nand2 or any combinatorial logic nand2 or any combinatorial logic nand2 or any combinatorial logic t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for a particular combinatorial cell fanout = 4 t pd t pd t pd 50% vcc v cc vcc 50% gnd a, b, c 50% 50% 50% (rr) (rf) gnd out out gnd 50% (ff) (fr) t pd t pd
igloo plus low power flash fpgas revision 11 2-53 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-80 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v combinatorial cell equation parameter std. units inv y = !a t pd 0.72 ns and2 y = a b t pd 0.86 ns nand2 y = !(a b) t pd 1.00 ns or2 y = a + b t pd 1.26 ns nor2 y = !(a + b) t pd 1.16 ns xor2 y = a bt pd 1.46 ns maj3 y = maj(a, b, c) t pd 1.47 ns xor3 y = a b ct pd 2.12 ns mux2 y = a !s + b s t pd 1.24 ns and3 y = a b c t pd 1.40 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-81 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v combinatorial cell equation parameter std. units inv y = !a t pd 1.26 ns and2 y = a b t pd 1.46 ns nand2 y = !(a b) t pd 1.78 ns or2 y = a + b t pd 2.47 ns nor2 y = !(a + b) t pd 2.17 ns xor2 y = a bt pd 2.62 ns maj3 y = maj(a, b, c) t pd 2.66 ns xor3 y = a b ct pd 3.77 ns mux2 y = a !s + b s t pd 2.20 ns and3 y = a b c t pd 2.49 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics 2-54 revision 11 versatile specifications as a sequential module the igloo plus library offers a wide variety of se quential cells, including flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the library. for more details, refer to the fusion, igloo/e, and proasic3/e macro library guide . figure 2-19 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
igloo plus low power flash fpgas revision 11 2-55 timing characteristics 1.5 v dc core voltage figure 2-20 ? timing model and waveforms pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-82 ? register delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t clkq clock-to-q of the core register 0.89 ns t sud data setup time for the core register 0.81 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 0.73 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.60 ns t pre2q asynchronous preset-to-q of the core register 0.62 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery time for the core register 0.24 ns t rempre asynchronous preset removal time for the core register 0.00 ns t recpre asynchronous preset recovery time for the core register 0.23 ns t wclr asynchronous clear minimum pulse width for the core register 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.56 ns t ckmpwl clock minimum pulse width low for the core register 0.56 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-56 revision 11 1.2 v dc core voltage table 2-83 ? register delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t clkq clock-to-q of the core register 1.61 ns t sud data setup time for the core register 1.17 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 1.29 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.87 ns t pre2q asynchronous preset-to-q of the core register 0.89 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery time for the core register 0.24 ns t rempre asynchronous preset removal time for the core register 0.00 ns t recpre asynchronous preset recovery time for the core register 0.24 ns t wclr asynchronous clear minimum pulse width for the core register 0.46 ns t wpre asynchronous preset minimum pulse width for the core register 0.46 ns t ckmpwh clock minimum pulse width high for the core register 0.95 ns t ckmpwl clock minimum pulse width low for the core register 0.95 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus low power flash fpgas revision 11 2-57 global resource characteristics aglp125 clock tree topology clock delays are device-specific. figure 2-21 is an example of a global tree used for clock routing. the global tree presented in figure 2-21 is driven by a ccc located on the west side of the aglp125 device. it is used to drive all d- flip-flops in the device. figure 2-21 ? example of global tree use in an aglp125 device for clock routing central global rib versatile rows global spine ccc
igloo plus dc and switching characteristics 2-58 revision 11 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-61 . ta b l e 2 - 8 4 to table 2-89 on page 2-60 present minimum and maximum global clock delays within each device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics 1.5 v dc core voltage table 2-84 ? aglp030 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.21 1.42 ns t rckh input high delay for global clock 1.23 1.49 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.27 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-85 ? aglp060 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.32 1.62 ns t rckh input high delay for global clock 1.34 1.72 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.38 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus low power flash fpgas revision 11 2-59 1.2 v dc core voltage table 2-86 ? aglp125 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.36 1.71 ns t rckh input high delay for global clock 1.39 1.82 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.43 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-87 ? aglp030 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.80 2.09 ns t rckh input high delay for global clock 1.88 2.27 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.39 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics 2-60 revision 11 table 2-88 ? aglp060 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.02 2.43 ns t rckh input high delay for global clock 2.09 2.65 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.56 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values. table 2-89 ? aglp125 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.08 2.54 ns t rckh input high delay for global clock 2.15 2.77 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.62 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus low power flash fpgas revision 11 2-61 clock conditioning circuits ccc electrical specifications timing characteristics table 2-90 ? igloo plus ccc/pll specification for igloo plus v2 or v5 devic es, 1.5 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 250 mhz clock conditioning circuitry output frequency f out_ccc 0.75 250 mhz delay increments in programmable delay blocks 1, 2 360 ps number of programmable values in each programmable delay block 32 serial clock (sclk) for dynamic pll 3,4 input cycle-to-cycle jitter (peak magnitude) 100 mhz acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 5 lockcontrol = 0 2.5 lockcontrol = 1 1.5 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 1.25 15.65 ns delay range in block: programmable delay 2 1, 2 0.469 15.65 ns delay range in block: fixed delay 1, 2 3.5 ns vco output peak-to-peak period jitter f ccc_out 6 maximum peak-to-peak period jitter 6,7,8 sso 2 sso 4 sso 8 sso 16 0.75 mhz to 50 mhz 0.50% 0.60% 0.80% 1.20% 50 mhz to 250 mhz 2.50% 4.00% 6.00% 12.00% notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-6 and table 2-7 on page 2-7 for deratings. 2. t j = 25c, v cc = 1.5 v 3. maximum value obtained for a std speed grade device in worst case commercial conditions. for specific junction temperature and voltage supply, refer to table 2-6 on page 2-6 and table 2-7 on page 2-7 for derating values. 4. the aglp030 device does not support a pll. 5. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to the pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter. 6. vco output jitter is calculated as a percentage of the vco frequency. the jitter (in ps) can be calculated by multiplying the vco period by the per cent jitter. the vco jitter (in ps) applies to ccc_out regardless of the output divider settings. for example, if the jitter on vco is 300 ps, the jitter on ccc_out is also 300 ps, regardless of the output divider settings. 7. measurements done with lvttl 3.3 v 8 ma i/o drive strength and high slew rate, vcc/vccpll = 1.14 v, vcci = 3.3 v, vq/pq/tq type of packages, 20 pf load. 8. sso are outputs that are synchronous to a single clock domain and have clock-to-out times that are within 200 ps of each other.switching i/os are placed outside of the pl l bank. refer to the "proasic3/e sso and pin placement guidelines" chapter of the proasic3 fpga fabric user?s guide .
igloo plus dc and switching characteristics 2-62 revision 11 table 2-91 ? igloo plus ccc/pll specification for igloo plus v2 devices, 1.2 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 160 mhz clock conditioning circuitry output frequency f out_ccc 0.75 160 mhz delay increments in programmable delay blocks 1, 2 580 ps number of programmable values in each programmable delay block 32 serial clock (sclk) for dynamic pll 3,4 input cycle-to-cycle jitt er (peak magnitude) 60 mhz acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 5 lockcontrol = 0 4 ns lockcontrol = 1 3 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 2.3 20.86 ns delay range in block: programmable delay 2 1, 2 0.025 20.86 ns delay range in block: fixed delay 1, 2 5.7 ns vco output peak-to-peak period jitter f ccc_out 6 maximum peak-to-peak period jitter 6,7,8 sso 2 sso 4 sso 8 sso 16 0.75 mhz to 50 mhz 0.50% 1.20% 2.00% 3.00% 50 mhz to 160 mhz 2.50% 5.00% 7.00% 15.00% notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-6 and table 2-7 on page 2-7 for deratings. 2. t j = 25c, v cc = 1.2 v 3. maximum value obtained for a std speed grade device in worst case commercial conditions.for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 and table 2-7 on page 2-7 for derating values. 4. the aglp030 device does not support pll. 5. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by period jitter parameter. 6. vco output jitter is calculated as a percentage of the vco frequency. the jitter (in ps) can be calculated by multiplying the vco period by the per cent jitter. the vco jitter (in ps) applies to ccc_out regardless of the output divider settings. for example, if the jitter on vco is 300 ps, the jitter on ccc_out is also 300 ps, regardless of the output divider settings. 7. measurements are done with lvttl 3.3 v, 8 ma, i/o drive strength and high slew rate. vcc/vccpll = 1.14 v, vcci = 3.3 v, vq/pq/tq type of packages, 20 pf load. 8. sso are outputs that are synchronous to a single clock domain, and have their clock-to-out times within 200 ps of each other. switching i/os are placed outside of the pll bank. refer to the "proasic3/e sso and pin placement guidelines" chapter of the proasic3 fpga fabric user?s guide.
igloo plus low power flash fpgas revision 11 2-63 note: peak-to-peak jitter meas urements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-22 ? peak-to-peak jitter definition t period_max t period_min output signal
igloo plus dc and switching characteristics 2-64 revision 11 embedded sram and fifo characteristics sram figure 2-23 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
igloo plus low power flash fpgas revision 11 2-65 timing waveforms figure 2-24 ? ram read for pass-through output figure 2-25 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
igloo plus dc and switching characteristics 2-66 revision 11 figure 2-26 ? ram write, output retained (wmode = 0) figure 2-27 ? ram write, output as wr ite data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (pass-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2
igloo plus low power flash fpgas revision 11 2-67 figure 2-28 ? write access after read onto same address figure 2-29 ? ram reset a 0 a 1 a 0 a 0 a 1 a 3 d 1 d 2 d 3 t ah t as t ah t as t ckq1 t ckq1 t ckq2 t cckh clk1 add1 wen_b1 do1 (pass-through) do1 (pipelined) clk2 add2 di2 wen_b2 d n d n d 0 d 1 d 0 clk reset_b do d n t cyc t ckh t ckl t rstbq d m
igloo plus dc and switching characteristics 2-68 revision 11 timing characteristics 1.5 v dc core voltage table 2-92 ? ram4k9 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t as address setup time 0.69 ns t ah address hold time 0.13 ns t ens ren_b, wen_b setup time 0.68 ns t enh ren_b, wen_b hold time 0.13 ns t bks blk_b setup time 1.37 ns t bkh blk_b hold time 0.13 ns t ds input data (di) setup time 0.59 ns t dh input data (di) hold time 0.30 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.94 ns clock high to new data valid on do (flow-through, wmode = 1) 2.55 ns t ckq2 clock high to new data valid on do (pipelined) 1.51 ns t c2cwwl address collision clk-to-clk delay for reliable write after write on same address ? applicable to closing edge 0.29 ns t c2crwh address collision clk-to-clk delay for reliable read access after write on same address ? applicable to opening edge 0.24 ns t c2cwrh address collision clk-to-clk delay for reliable write access after read on same address ? applicable to opening edge 0.40 ns t rstbq reset_b low to data out low on do (flow-through) 1.72 ns reset_b low to data out low on do (pipelined) 1.72 ns t remrstb reset_b removal 0.51 ns t recrstb reset_b recovery 2.68 ns t mpwrstb reset_b minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency 160 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus low power flash fpgas revision 11 2-69 table 2-93 ? ram512x18 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t as address setup time 0.69 ns t ah address hold time 0.13 ns t ens ren_b, wen_b setup time 0.61 ns t enh ren_b, wen_b hold time 0.07 ns t ds input data (di) setup time 0.59 ns t dh input data (di) hold time 0.30 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 3.51 ns t ckq2 clock high to new data valid on do (pipelined) 1.43 ns t c2crwh address collision clk-to-clk delay for reliable read access after write on same address ? applicable to opening edge 0.21 ns t c2cwrh address collision clk-to-clk delay for reliable write access after read on same address ? applicable to opening edge 0.25 ns t rstbq reset_b low to data out low on do (flow-through) 1.72 ns reset_b low to data out low on do (pipelined) 1.72 ns t remrstb reset_b removal 0.51 ns t recrstb reset_b recovery 2.68 ns t mpwrstb reset_b minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency 160 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-70 revision 11 1.2 v dc core voltage table 2-94 ? ram4k9 commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t as address setup time 1.28 ns t ah address hold time 0.25 ns t ens ren_b, wen_b setup time 1.25 ns t enh ren_b, wen_b hold time 0.25 ns t bks blk_b setup time 2.54 ns t bkh blk_b hold time 0.25 ns t ds input data (di) setup time 1.10 ns t dh input data (di) hold time 0.55 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 5.51 ns clock high to new data valid on do (flow-through, wmode = 1) 4.77 ns t ckq2 clock high to new data valid on do (pipelined) 2.82 ns t c2cwwl address collision clk-to-clk delay for re liable write after write on same address ? applicable to closing edge 0.30 ns t c2crwh address collision clk-to-clk delay for reliable read access after write on same address ? applicable to opening edge 0.32 ns t c2cwrh address collision clk-to-clk delay for reliable write access after read on same address ? applicable to opening edge 0.44 ns t rstbq reset_b low to data out low on do (flow-through) 3.21 ns reset_b low to data out low on do (pipelined) 3.21 ns t remrstb reset_b removal 0.93 ns t recrstb reset_b recovery 4.94 ns t mpwrstb reset_b minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency 92 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus low power flash fpgas revision 11 2-71 table 2-95 ? ram512x18 commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t as address setup time 1.28 ns t ah address hold time 0.25 ns t ens ren_b, wen_b setup time 1.13 ns t enh ren_b, wen_b hold time 0.13 ns t ds input data (di) setup time 1.10 ns t dh input data (di) hold time 0.55 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 6.56 ns t ckq2 clock high to new data valid on do (pipelined) 2.67 ns t c2crwh address collision clk-to-clk delay for relia ble read access after wr ite on same address ? applicable to opening edge 0.29 ns t c2cwrh address collision clk-to-clk delay for reliabl e write access after r ead on same address ? applicable to opening edge 0.36 ns t rstbq reset_b low to data out low on do (flow through) 3.21 ns reset_b low to data out low on do (pipelined) 3.21 ns t remrstb reset_b removal 0.93 ns t recrstb reset_b recovery 4.94 ns t mpwrstb reset_b minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency 92 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics 2-72 revision 11 fifo figure 2-30 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
igloo plus low power flash fpgas revision 11 2-73 timing waveforms figure 2-31 ? fifo reset figure 2-32 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
igloo plus dc and switching characteristics 2-74 revision 11 figure 2-33 ? fifo full flag and afull flag assertion figure 2-34 ? fifo empty flag and aempty flag deassertion figure 2-35 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
igloo plus low power flash fpgas revision 11 2-75 timing characteristics 1.5 v dc core voltage table 2-96 ? fifo worst commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units t ens ren_b, wen_b setup time 1.66 ns t enh ren_b, wen_b hold time 0.13 ns t bks blk_b setup time 0.30 ns t bkh blk_b hold time 0.00 ns t ds input data (di) setup time 0.63 ns t dh input data (di) hold time 0.20 ns t ckq1 clock high to new data valid on do (flow-through) 2.77 ns t ckq2 clock high to new data valid on do (pipelined) 1.50 ns t rckef rclk high to empty flag valid 2.94 ns t wckff wclk high to full flag valid 2.79 ns t ckaf clock high to almost empty/full flag valid 10.71 ns t rstfg reset_b low to empty/ full flag valid 2.90 ns t rstaf reset_b low to almost empty/full flag valid 10.60 ns t rstbq reset_b low to data out low on do (flow-through) 1.68 ns reset_b low to data out low on do (pipelined) 1.68 ns t remrstb reset_b removal 0.51 ns t recrstb reset_b recovery 2.68 ns t mpwrstb reset_b minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency for fifo 160 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-76 revision 11 1.2 v dc core voltage table 2-97 ? fifo worst commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units t ens ren_b, wen_b setup time 3.44 ns t enh ren_b, wen_b hold time 0.26 ns t bks blk_b setup time 0.30 ns t bkh blk_b hold time 0.00 ns t ds input data (di) setup time 1.30 ns t dh input data (di) hold time 0.41 ns t ckq1 clock high to new data valid on do (flow-through) 5.67 ns t ckq2 clock high to new data valid on do (pipelined) 3.02 ns t rckef rclk high to empty flag valid 6.02 ns t wckff wclk high to full flag valid 5.71 ns t ckaf clock high to almost empty/full flag valid 22.17 ns t rstfg reset_b low to empty/ full flag valid 5.93 ns t rstaf reset_b low to almost empty/full flag valid 21.94 ns t rstbq reset_b low to data out low on do (flow-through) 3.41 ns reset_b low to data out low on do (pipelined) 3.41 ns t remrstb reset_b removal 1.02 ns t recrstb reset_b recovery 5.48 ns t mpwrstb reset_b minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency for fifo 92 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus low power flash fpgas revision 11 2-77 embedded flashrom characteristics timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage figure 2-36 ? timing diagram a 0 a 1 t su t hold t su t hold t su t hold t ckq2 t ckq2 t ckq2 clk a ddress data d 0 d 0 d 1 table 2-98 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units t su address setup time 0.57 ns t hold address hold time 0.00 ns t ck2q clock to out 17.58 ns f max maximum clock frequency 15 mhz table 2-99 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units t su address setup time 0.59 ns t hold address hold time 0.00 ns t ck2q clock to out 30.94 ns f max maximum clock frequency 10 mhz
igloo plus dc and switching characteristics 2-78 revision 11 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtai n complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/o characteristics" section on page 2-15 for more details. timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-100 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t disu test data input setup time 1.00 ns t dihd test data input hold time 2.00 ns t tmssu test mode select setup time 1.00 ns t tmdhd test mode select hold time 2.00 ns t tck2q clock to q (data out) 8.00 ns t rstb2q reset to q (data out) 25.00 ns f tckmax tck maximum frequency 15 mhz t trstrem resetb removal time 0.58 ns t trstrec resetb recovery time 0.00 ns t trstmpw resetb minimum pulse tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-101 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t disu test data input setup time 1.50 ns t dihd test data input hold time 3.00 ns t tmssu test mode select setup time 1.50 ns t tmdhd test mode select hold time 3.00 ns t tck2q clock to q (data out) 11.00 ns t rstb2q reset to q (data out) 30.00 ns f tckmax tck maximum frequency 9.00 mhz t trstrem resetb removal time 1.18 ns t trstrec resetb recovery time 0.00 ns t trstmpw resetb minimum pulse tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus low power flash fpgas revision 11 2-79 actel safety critical, life support, and high-reliability applications policy the actel products described in this advance st atus datasheet may not have completed actel?s qualification process. actel may amend or enhanc e products during the pr oduct introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any actel pr oduct (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult actel?s terms and conditions for specific liab ility exclusions relating to life-support applications. a reliability report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for additional reliability information.

revision 11 3-1 igloo plus low power flash fpgas 3 ? package pin assignments 128-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . pin information is in the "pin descriptions" chapter of the igloo plus fpga fabric user?s guide . note: this is the bottom view of the package. 1 128-pin vqfp 128
package pin assignments 3-2 revision 11 128-pin vqfp pin number aglp030 function 1 io119rsb3 2 io118rsb3 3 io117rsb3 4 io115rsb3 5 io116rsb3 6 io113rsb3 7 io114rsb3 8gnd 9vccib3 10 io112rsb3 11 io111rsb3 12 io110rsb3 13 io109rsb3 14 gec0/io108rsb3 15 gea0/io107rsb3 16 geb0/io106rsb3 17 vcc 18 io104rsb3 19 io103rsb3 20 io102rsb3 21 io101rsb3 22 io100rsb3 23 io99rsb3 24 gnd 25 vccib3 26 io97rsb3 27 io98rsb3 28 io95rsb3 29 io96rsb3 30 io94rsb3 31 io93rsb3 32 io92rsb3 33 io91rsb2 34 ff/io90rsb2 35 io89rsb2 36 io88rsb2 37 io86rsb2 38 io84rsb2 39 io83rsb2 40 gnd 41 vccib2 42 io82rsb2 43 io81rsb2 44 io79rsb2 45 io78rsb2 46 io77rsb2 47 io75rsb2 48 io74rsb2 49 vcc 50 io73rsb2 51 io72rsb2 52 io70rsb2 53 io69rsb2 54 io68rsb2 55 io66rsb2 56 io65rsb2 57 gnd 58 vccib2 59 io63rsb2 60 io61rsb2 61 io59rsb2 62 tck 63 tdi 64 tms 65 vpump 66 tdo 67 trst 68 io58rsb1 69 vjtag 70 io56rsb1 128-pin vqfp pin number aglp030 function 71 io57rsb1 72 vccib1 73 gnd 74 io55rsb1 75 io54rsb1 76 io53rsb1 77 io52rsb1 78 io51rsb1 79 io50rsb1 80 io49rsb1 81 vcc 82 gdb0/io48rsb1 83 gda0/io47rsb1 84 gdc0/io46rsb1 85 io45rsb1 86 io44rsb1 87 io43rsb1 88 io42rsb1 89 vccib1 90 gnd 91 io40rsb1 92 io41rsb1 93 io39rsb1 94 io38rsb1 95 io37rsb1 96 io36rsb1 97 io35rsb0 98 io34rsb0 99 io33rsb0 100 io32rsb0 101 io30rsb0 102 io28rsb0 103 io27rsb0 104 vccib0 105 gnd 128-pin vqfp pin number aglp030 function
igloo plus low power flash fpgas revision 11 3-3 106 io26rsb0 107 io25rsb0 108 io23rsb0 109 io22rsb0 110 io21rsb0 111 io19rsb0 112 io18rsb0 113 vcc 114 io17rsb0 115 io16rsb0 116 io14rsb0 117 io13rsb0 118 io12rsb0 119 io10rsb0 120 io09rsb0 121 vccib0 122 gnd 123 io07rsb0 124 io05rsb0 125 io03rsb0 126 io02rsb0 127 io01rsb0 128 io00rsb0 128-pin vqfp pin number aglp030 function
package pin assignments 3-4 revision 11 176-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: this is the bottom view of the package. 1 176-pin vqfp 176
igloo plus low power flash fpgas revision 11 3-5 176-pin vqfp pin number aglp060 function 1 gaa2/io156rsb3 2 io155rsb3 3 gab2/io154rsb3 4 io153rsb3 5 gac2/io152rsb3 6gnd 7 vccib3 8 io149rsb3 9 io147rsb3 10 io145rsb3 11 io144rsb3 12 io143rsb3 13 vcc 14 io141rsb3 15 gfc1/io140rsb3 16 gfb1/io138rsb3 17 gfb0/io137rsb3 18 vcomplf 19 gfa1/io136rsb3 20 vccplf 21 gfa0/io135rsb3 22 gnd 23 vccib3 24 gfa2/io134rsb3 25 gfb2/io133rsb3 26 gfc2/io132rsb3 27 io131rsb3 28 io130rsb3 29 io129rsb3 30 io127rsb3 31 io126rsb3 32 io125rsb3 33 io123rsb3 34 io122rsb3 35 io121rsb3 36 io119rsb3 37 gnd 38 vccib3 39 gec1/io116rsb3 40 geb1/io114rsb3 41 gec0/io115rsb3 42 geb0/io113rsb3 43 gea1/io112rsb3 44 gea0/io111rsb3 45 gea2/io110rsb2 46 nc 47 ff/geb2/io109r sb2 48 gec2/io108rsb2 49 io106rsb2 50 io107rsb2 51 io104rsb2 52 io105rsb2 53 io102rsb2 54 io103rsb2 55 gnd 56 vccib2 57 io101rsb2 58 io100rsb2 59 io99rsb2 60 io98rsb2 61 io97rsb2 62 io96rsb2 63 io95rsb2 64 io94rsb2 65 io93rsb2 66 vcc 67 io92rsb2 68 io91rsb2 69 io90rsb2 176-pin vqfp pin number aglp060 function 70 io89rsb2 71 io88rsb2 72 io87rsb2 73 io86rsb2 74 io85rsb2 75 io84rsb2 76 gnd 77 vccib2 78 io83rsb2 79 io82rsb2 80 gdc2/io80rsb2 81 io81rsb2 82 gda2/io78rsb2 83 gdb2/io79rsb2 84 nc 85 nc 86 tck 87 tdi 88 tms 89 vpump 90 tdo 91 trst 92 vjtag 93 gda1/io76rsb1 94 gdc0/io73rsb1 95 gdb1/io74rsb1 96 gdc1/io72rsb1 97 vccib1 98 gnd 99 io70rsb1 100 io69rsb1 101 io67rsb1 102 io66rsb1 103 io65rsb1 104 io63rsb1 176-pin vqfp pin number aglp060 function
package pin assignments 3-6 revision 11 105 io62rsb1 106 io61rsb1 107 gcc2/io60rsb1 108 gcb2/io59rsb1 109 gca2/io58rsb1 110 gca0/io57rsb1 111 gca1/io56rsb1 112 vccib1 113 gnd 114 gcb0/io55rsb1 115 gcb1/io54rsb1 116 gcc0/io53rsb1 117 gcc1/io52rsb1 118 io51rsb1 119 io50rsb1 120 vcc 121 io48rsb1 122 io47rsb1 123 io45rsb1 124 io44rsb1 125 io43rsb1 126 vccib1 127 gnd 128 gbc2/io40rsb1 129 io39rsb1 130 gbb2/io38rsb1 131 io37rsb1 132 gba2/io36rsb1 133 gba1/io35rsb0 134 nc 135 gba0/io34rsb0 136 nc 137 gbb1/io33rsb0 138 nc 139 gbc1/io31rsb0 176-pin vqfp pin number aglp060 function 140 gbb0/io32rsb0 141 gbc0/io30rsb0 142 io29rsb0 143 io28rsb0 144 io27rsb0 145 vccib0 146 gnd 147 io26rsb0 148 io25rsb0 149 io24rsb0 150 io23rsb0 151 io22rsb0 152 io21rsb0 153 io20rsb0 154 io19rsb0 155 io18rsb0 156 vcc 157 io17rsb0 158 io16rsb0 159 io15rsb0 160 io14rsb0 161 io13rsb0 162 io12rsb0 163 io11rsb0 164 io10rsb0 165 io09rsb0 166 vccib0 167 gnd 168 io07rsb0 169 io08rsb0 170 gac1/io05rsb0 171 io06rsb0 172 gab1/io03rsb0 173 gac0/io04rsb0 174 gab0/io02rsb0 176-pin vqfp pin number aglp060 function 175 gaa1/io01rsb0 176 gaa0/io00rsb0 176-pin vqfp pin number aglp060 function
igloo plus low power flash fpgas revision 11 3-7 201-pin csp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: this is the bottom view of the package. 1 a b c d e f g h j k l m n p r 2 3 4 5 6 7 8 9 15 14 13 12 11 10
package pin assignments 3-8 revision 11 201-pin csp pin number aglp030 function a1 nc a2 io04rsb0 a3 io06rsb0 a4 io09rsb0 a5 io11rsb0 a6 io13rsb0 a7 io17rsb0 a8 io18rsb0 a9 io24rsb0 a10 io26rsb0 a11 io27rsb0 a12 io31rsb0 a13 nc a14 nc a15 nc b1 nc b2 nc b3 io08rsb0 b4 io05rsb0 b5 io07rsb0 b6 io15rsb0 b7 io14rsb0 b8 io16rsb0 b9 io20rsb0 b10 io22rsb0 b11 io34rsb0 b12 io29rsb0 b13 nc b14 nc b15 nc c1 nc c2 nc c3 gnd c4 io00rsb0 c5 io02rsb0 c6 io12rsb0 c7 io23rsb0 c8 io19rsb0 c9 io28rsb0 c10 io32rsb0 c11 io35rsb0 c12 nc c13 gnd c14 io41rsb1 c15 io37rsb1 d1 io117rsb3 d2 io118rsb3 d3 nc d4 gnd d5 io01rsb0 d6 io03rsb0 d7 io10rsb0 d8 io21rsb0 d9 io25rsb0 d10 io30rsb0 d11 io33rsb0 d12 gnd d13 nc d14 io36rsb1 d15 io39rsb1 e1 io115rsb3 e2 io114rsb3 e3 nc e4 nc e12 nc e13 nc e14 gdc0/io46rsb1 e15 gdb0/io48rsb1 f1 io113rsb3 f2 io116rsb3 201-pin csp pin number aglp030 function f3 io119rsb3 f4 io111rsb3 f6 gnd f7 vcc f8 vccib0 f9 vccib0 f10 vccib0 f12 nc f13 nc f14 io40rsb1 f15 io38rsb1 g1 nc g2 io112rsb3 g3 io110rsb3 g4 io109rsb3 g6 vccib3 g7 gnd g8 vcc g9 gnd g10 gnd g12 nc g13 nc g14 io42rsb1 g15 io44rsb1 h1 nc h2 geb0/io106rsb3 h3 gec0/io108rsb3 h4 nc h6 vccib3 h7 gnd h8 vcc h9 gnd h10 vccib1 h12 io54rsb1 h13 gda0/io47rsb1 201-pin csp pin number aglp030 function
igloo plus low power flash fpgas revision 11 3-9 h14 io45rsb1 h15 io43rsb1 j1 gea0/io107rsb3 j2 io105rsb3 j3 io104rsb3 j4 io102rsb3 j6 vccib3 j7 gnd j8 vcc j9 gnd j10 vccib1 j12 nc j13 nc j14 io52rsb1 j15 io50rsb1 k1 io103rsb3 k2 io101rsb3 k3 io99rsb3 k4 io100rsb3 k6 gnd k7 vccib2 k8 vccib2 k9 vccib2 k10 vccib1 k12 nc k13 io57rsb1 k14 io49rsb1 k15 io53rsb1 l1 io96rsb3 l2 io98rsb3 l3 io95rsb3 l4 io94rsb3 l12 nc l13 nc l14 io51rsb1 201-pin csp pin number aglp030 function l15 io58rsb1 m1 io93rsb3 m2 io92rsb3 m3 io97rsb3 m4 gnd m5 nc m6 io79rsb2 m7 io77rsb2 m8 io72rsb2 m9 io70rsb2 m10 io61rsb2 m11 io59rsb2 m12 gnd m13 nc m14 io55rsb1 m15 io56rsb1 n1 nc n2 nc n3 gnd n4 nc n5 io88rsb2 n6 io81rsb2 n7 io75rsb2 n8 io68rsb2 n9 io66rsb2 n10 io65rsb2 n11 io71rsb2 n12 io63rsb2 n13 gnd n14 tdo n15 vjtag p1 nc p2 nc p3 nc p4 nc 201-pin csp pin number aglp030 function p5 io87rsb2 p6 io86rsb2 p7 io84rsb2 p8 io80rsb2 p9 io74rsb2 p10 io73rsb2 p11 io76rsb2 p12 io67rsb2 p13 io64rsb2 p14 vpump p15 trst r1 nc r2 nc r3 io91rsb2 r4 ff/io90rsb2 r5 io89rsb2 r6 io83rsb2 r7 io82rsb2 r8 io85rsb2 r9 io78rsb2 r10 io69rsb2 r11 io62rsb2 r12 io60rsb2 r13 tms r14 tdi r15 tck 201-pin csp pin number aglp030 function
package pin assignments 3-10 revision 11 201-pin csp pin number aglp060 function a1 io150rsb3 a2 gaa0/io00rsb0 a3 gac0/io04rsb0 a4 io08rsb0 a5 io11rsb0 a6 io15rsb0 a7 io17rsb0 a8 io18rsb0 a9 io22rsb0 a10 io26rsb0 a11 io29rsb0 a12 gbc1/io31rsb0 a13 gba2/io36rsb1 a14 io41rsb1 a15 nc b1 io151rsb3 b2 gab2/io154rsb3 b3 io06rsb0 b4 io09rsb0 b5 io13rsb0 b6 io10rsb0 b7 io12rsb0 b8 io20rsb0 b9 io23rsb0 b10 io25rsb0 b11 io24rsb0 b12 io27rsb0 b13 io37rsb1 b14 io46rsb1 b15 io42rsb1 c1 io155rsb3 c2 gaa2/io156rsb3 c3 gnd c4 gaa1/io01rsb0 c5 gab1/io03rsb0 c6 io07rsb0 c7 io16rsb0 c8 io21rsb0 c9 io28rsb0 c10 gbb1/io33rsb0 c11 gba1/io35rsb0 c12 gbb2/io38rsb1 c13 gnd c14 io48rsb1 c15 io39rsb1 d1 io146rsb3 d2 io144rsb3 d3 io148rsb3 d4 gnd d5 gab0/io02rsb0 d6 gac1/io05rsb0 d7 io14rsb0 d8 io19rsb0 d9 gbc0/io30rsb0 d10 gbb0/io32rsb0 d11 gba0/io34rsb0 d12 gnd d13 gbc2/io40rsb1 d14 io51rsb1 d15 io44rsb1 e1 io142rsb3 e2 io149rsb3 e3 io153rsb3 e4 gac2/io152rsb3 e12 io43rsb1 e13 io49rsb1 e14 gcc0/io53rsb1 e15 gcb0/io55rsb1 f1 io141rsb3 f2 gfc1/io140rsb3 201-pin csp pin number aglp060 function f3 io145rsb3 f4 io147rsb3 f6 gnd f7 vcc f8 vccib0 f9 vccib0 f10 vccib0 f12 io47rsb1 f13 io45rsb1 f14 gcc1/io52rsb1 f15 gca1/io56rsb1 g1* vcomplf g2 gfb0/io137rsb3 g3 gfc0/io139rsb3 g4 io143rsb3 g6 vccib3 g7 gnd g8 vcc g9 gnd g10 gnd g12 io50rsb1 g13 gcb1/io54rsb1 g14 gcc2/io60rsb1 g15 gca2/io58rsb1 h1* vccplf h2 gfa1/io136rsb3 h3 gfb1/io138rsb3 h4 nc h6 vccib3 h7 gnd h8 vcc h9 gnd h10 vccib1 h12 gcb2/io59rsb1 h13 gca0/io57rsb1 201-pin csp pin number aglp060 function * pin numbers g1 and h1 must be connected to grou nd because a pll is not su pported for aglp060-cs/g201.
igloo plus low power flash fpgas revision 11 3-11 h14 io64rsb1 h15 io62rsb1 j1 gfa2/io134rsb3 j2 gfa0/io135rsb3 j3 gfb2/io133rsb3 j4 io131rsb3 j6 vccib3 j7 gnd j8 vcc j9 gnd j10 vccib1 j12 io61rsb1 j13 io63rsb1 j14 io68rsb1 j15 io66rsb1 k1 io130rsb3 k2 gfc2/io132rsb3 k3 io127rsb3 k4 io129rsb3 k6 gnd k7 vccib2 k8 vccib2 k9 vccib2 k10 vccib1 k12 io65rsb1 k13 io67rsb1 k14 io69rsb1 k15 io70rsb1 l1 io126rsb3 l2 io128rsb3 l3 io121rsb3 l4 io123rsb3 l12 gdb1/io74rsb1 l13 gdc1/io72rsb1 l14 io71rsb1 201-pin csp pin number aglp060 function l15 gdc0/io73rsb1 m1 io122rsb3 m2 io124rsb3 m3 io119rsb3 m4 gnd m5 io125rsb3 m6 io98rsb2 m7 io96rsb2 m8 io91rsb2 m9 io89rsb2 m10 io82rsb2 m11 gda2/io78rsb2 m12 gnd m13 gda1/io76rsb1 m14 gda0/io77rsb1 m15 gdb0/io75rsb1 n1 io117rsb3 n2 io120rsb3 n3 gnd n4 geb1/io114rsb3 n5 io107rsb2 n6 io100rsb2 n7 io94rsb2 n8 io87rsb2 n9 io85rsb2 n10 gdc2/io80rsb2 n11 io90rsb2 n12 io84rsb2 n13 gnd n14 tdo n15 vjtag p1 gec0/io115rsb3 p2 gec1/io116rsb3 p3 gea0/io111rsb3 p4 gea1/io112rsb3 201-pin csp pin number aglp060 function p5 io106rsb2 p6 io105rsb2 p7 io103rsb2 p8 io99rsb2 p9 io93rsb2 p10 io92rsb2 p11 io95rsb2 p12 io86rsb2 p13 io83rsb2 p14 vpump p15 trst r1 io118rsb3 r2 geb0/io113rsb3 r3 gea2/io110rsb2 r4 ff/geb2/io109rs b2 r5 gec2/io108rsb2 r6 io102rsb2 r7 io101rsb2 r8 io104rsb2 r9 io97rsb2 r10 io88rsb2 r11 io81rsb2 r12 gdb2/io79rsb2 r13 tms r14 tdi r15 tck 201-pin csp pin number aglp060 function
package pin assignments 3-12 revision 11 281-pin csp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx note: this is the bottom view of the package. 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 m n p r t u v w d e f a b c g h j k l
igloo plus low power flash fpgas revision 11 3-13 281-pin csp pin number aglp125 function a1 gnd a2 gab0/io02rsb0 a3 gac1/io05rsb0 a4 io09rsb0 a5 io13rsb0 a6 io15rsb0 a7 io18rsb0 a8 io23rsb0 a9 io25rsb0 a10 vccib0 a11 io33rsb0 a12 io41rsb0 a13 io43rsb0 a14 io46rsb0 a15 io55rsb0 a16 io56rsb0 a17 gbc1/io58rsb0 a18 gba0/io61rsb0 a19 gnd b1 gaa2/io211rsb3 b2 vccib0 b3 gab1/io03rsb0 b4 gac0/io04rsb0 b5 io11rsb0 b6 gnd b7 io21rsb0 b8 io22rsb0 b9 io28rsb0 b10 io32rsb0 b11 io36rsb0 b12 io39rsb0 b13 io42rsb0 b14 gnd b15 io52rsb0 b16 gbc0/io57rsb0 b17 gba1/io62rsb0 b18 vccib1 b19 io64rsb1 c1 gab2/io209rsb3 c2 io210rsb3 c6 io12rsb0 c14 io47rsb0 c18 io54rsb0 c19 gbb2/io65rsb1 d1 io206rsb3 d2 io208rsb3 d4 gaa0/io00rsb0 d5 gaa1/io01rsb0 d6 io10rsb0 d7 io17rsb0 d8 io24rsb0 d9 io27rsb0 d10 gnd d11 io31rsb0 d12 io40rsb0 d13 io49rsb0 d14 io45rsb0 d15 gbb0/io59rsb0 d16 gba2/io63rsb1 d18 gbc2/io67rsb1 d19 io66rsb1 e1 io203rsb3 e2 io205rsb3 e4 io07rsb0 e5 io06rsb0 e6 io14rsb0 e7 io20rsb0 e8 io29rsb0 e9 io34rsb0 e10 io30rsb0 e11 io37rsb0 e12 io38rsb0 281-pin csp pin number aglp125 function e13 io48rsb0 e14 gbb1/io60rsb0 e15 io53rsb0 e16 io69rsb1 e18 io68rsb1 e19 io71rsb1 f1 io198rsb3 f2 gnd f3 io201rsb3 f4 io204rsb3 f5 io16rsb0 f15 io50rsb0 f16 io74rsb1 f17 io72rsb1 f18 gnd f19 io73rsb1 g1 io195rsb3 g2 io200rsb3 g4 io202rsb3 g5 io08rsb0 g7 gac2/io207rsb3 g8 vccib0 g9 io26rsb0 g10 io35rsb0 g11 io44rsb0 g12 vccib0 g13 io51rsb0 g15 io70rsb1 g16 io75rsb1 g18 gcc0/io80rsb1 g19 gcb1/io81rsb1 h1 gfb0/io191rsb3 h2 io196rsb3 h4 gfc1/io194rsb3 h5 gfb1/io192rsb3 h7 vccib3 281-pin csp pin number aglp125 function
package pin assignments 3-14 revision 11 h8 vcc h9 vccib0 h10 vcc h11 vccib0 h12 vcc h13 vccib1 h15 io77rsb1 h16 gcb0/io82rsb1 h18 gca1/io83rsb1 h19 gca2/io85rsb1 j1 vcomplf j2 gfa0/io189rsb3 j4 vccplf j5 gfc0/io193rsb3 j7 gfa2/io188rsb3 j8 vccib3 j9 gnd j10 gnd j11 gnd j12 vccib1 j13 gcc1/io79rsb1 j15 gca0/io84rsb1 j16 gcb2/io86rsb1 j18 io76rsb1 j19 io78rsb1 k1 vccib3 k2 gfa1/io190rsb3 k4 gnd k5 io19rsb0 k7 io197rsb3 k8 vcc k9 gnd k10 gnd k11 gnd k12 vcc k13 gcc2/io87rsb1 281-pin csp pin number aglp125 function k15 io89rsb1 k16 gnd k18 io88rsb1 k19 vccib1 l1 gfb2/io187rsb3 l2 io185rsb3 l4 gfc2/io186rsb3 l5 io184rsb3 l7 io199rsb3 l8 vccib3 l9 gnd l10 gnd l11 gnd l12 vccib1 l13 io95rsb1 l15 io91rsb1 l16 nc l18 io90rsb1 l19 nc m1 io180rsb3 m2 io179rsb3 m4 io181rsb3 m5 io183rsb3 m7 vccib3 m8 vcc m9 vccib2 m10 vcc m11 vccib2 m12 vcc m13 vccib1 m15 io122rsb2 m16 io93rsb1 m18 io92rsb1 m19 nc n1 io178rsb3 n2 io175rsb3 281-pin csp pin number aglp125 function n4 io182rsb3 n5 io161rsb2 n7 gea2/io164rsb2 n8 vccib2 n9 io137rsb2 n10 io135rsb2 n11 io131rsb2 n12 vccib2 n13 vpump n15 io117rsb2 n16 io96rsb1 n18 io98rsb1 n19 io94rsb1 p1 io174rsb3 p2 gnd p3 io176rsb3 p4 io177rsb3 p5 gea0/io165rsb3 p15 io111rsb2 p16 io108rsb2 p17 gdc1/io99rsb1 p18 gnd p19 io97rsb1 r1 io173rsb3 r2 io172rsb3 r4 gec1/io170rsb3 r5 geb1/io168rsb3 r6 io154rsb2 r7 io149rsb2 r8 io146rsb2 r9 io138rsb2 r10 io134rsb2 r11 io132rsb2 r12 io130rsb2 r13 io118rsb2 r14 io112rsb2 281-pin csp pin number aglp125 function
igloo plus low power flash fpgas revision 11 3-15 r15 io109rsb2 r16 gda1/io103rsb1 r18 gdb0/io102rsb1 r19 gdc0/io100rsb1 t1 io171rsb3 t2 gec0/io169rsb3 t4 geb0/io167rsb3 t5 io157rsb2 t6 io158rsb2 t7 io148rsb2 t8 io145rsb2 t9 io143rsb2 t10 gnd t11 io129rsb2 t12 io126rsb2 t13 io125rsb2 t14 io116rsb2 t15 gdc2/io107rsb2 t16 tms t18 vjtag t19 gdb1/io101rsb1 u1 io160rsb2 u2 gea1/io166rsb3 u6 io151rsb2 u14 io121rsb2 u18 trst u19 gda0/io104rsb1 v1 io159rsb2 v2 vccib3 v3 gec2/io162rsb2 v4 io156rsb2 v5 io153rsb2 v6 gnd v7 io144rsb2 v8 io141rsb2 v9 io140rsb2 281-pin csp pin number aglp125 function v10 io133rsb2 v11 io127rsb2 v12 io123rsb2 v13 io120rsb2 v14 gnd v15 io113rsb2 v16 gda2/io105rsb2 v17 tdi v18 vccib2 v19 tdo w1 gnd w2 ff/geb2/io163rsb 2 w3 io155rsb2 w4 io152rsb2 w5 io150rsb2 w6 io147rsb2 w7 io142rsb2 w8 io139rsb2 w9 io136rsb2 w10 vccib2 w11 io128rsb2 w12 io124rsb2 w13 io119rsb2 w14 io115rsb2 w15 io114rsb2 w16 io110rsb2 w17 gdb2/io106rsb2 w18 tck w19 gnd 281-pin csp pin number aglp125 function
package pin assignments 3-16 revision 11 289-pin csp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: this is the bottom view of the package. 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u a1 ball pad corner
igloo plus low power flash fpgas revision 11 3-17 289-pin csp pin number aglp030 function a1 io03rsb0 a2 nc a3 nc a4 gnd a5 io10rsb0 a6 io14rsb0 a7 io16rsb0 a8 io18rsb0 a9 gnd a10 io23rsb0 a11 io27rsb0 a12 nc a13 nc a14 gnd a15 nc a16 nc a17 io30rsb0 b1 io01rsb0 b2 gnd b3 nc b4 nc b5 io07rsb0 b6 nc b7 vccib0 b8 io17rsb0 b9 io19rsb0 b10 io24rsb0 b11 io28rsb0 b12 vccib0 b13 nc b14 nc b15 nc b16 io31rsb0 b17 gnd c1 nc c2 io00rsb0 c3 io04rsb0 c4 nc c5 vccib0 c6 io09rsb0 c7 io13rsb0 c8 io15rsb0 c9 io21rsb0 c10 gnd c11 io29rsb0 c12 nc c13 nc c14 nc c15 gnd c16 io34rsb0 c17 nc d1 nc d2 io119rsb3 d3 gnd d4 io02rsb0 d5 nc d6 nc d7 nc d8 gnd d9 io20rsb0 d10 io25rsb0 d11 nc d12 nc d13 gnd d14 io32rsb0 d15 io35rsb0 d16 nc d17 nc e1 vccib3 e2 io114rsb3 e3 io115rsb3 e4 io118rsb3 e5 io05rsb0 e6 nc 289-pin csp pin number aglp030 function e7 io06rsb0 e8 io11rsb0 e9 io22rsb0 e10 io26rsb0 e11 vccib0 e12 nc e13 io33rsb0 e14 io36rsb1 e15 io38rsb1 e16 vccib1 e17 nc f1 io111rsb3 f2 nc f3 io116rsb3 f4 vccib3 f5 io117rsb3 f6 nc f7 nc f8 io08rsb0 f9 io12rsb0 f10 nc f11 nc f12 nc f13 nc f14 gnd f15 nc f16 io37rsb1 f17 io41rsb1 g1 io110rsb3 g2 gnd g3 io113rsb3 g4 nc g5 nc g6 nc g7 gnd g8 gnd g9 vcc 289-pin csp pin number aglp030 function
package pin assignments 3-18 revision 11 g10 gnd g11 gnd g12 io40rsb1 g13 nc g14 io39rsb1 g15 io44rsb1 g16 nc g17 gnd h1 nc h2 gec0/io108rsb3 h3 nc h4 io112rsb3 h5 nc h6 io109rsb3 h7 gnd h8 gnd h9 gnd h10 gnd h11 gnd h12 nc h13 nc h14 io45rsb1 h15 vccib1 h16 gdb0/io48rsb1 h17 io42rsb1 j1 nc j2 gea0/io107rsb3 j3 vccib3 j4 io105rsb3 j5 nc j6 nc j7 vcc j8 gnd j9 gnd j10 gnd j11 vcc j12 io50rsb1 289-pin csp pin number aglp030 function j13 io43rsb1 j14 io51rsb1 j15 io52rsb1 j16 gdc0/io46rsb1 j17 gda0/io47rsb1 k1 gnd k2 geb0/io106rsb3 k3 io102rsb3 k4 io104rsb3 k5 io99rsb3 k6 nc k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 nc k13 nc k14 nc k15 io53rsb1 k16 gnd k17 io49rsb1 l1 io103rsb3 l2 io101rsb3 l3 nc l4 gnd l5 nc l6 nc l7 gnd l8 gnd l9 vcc l10 gnd l11 gnd l12 io58rsb1 l13 io54rsb1 l14 vccib1 l15 nc 289-pin csp pin number aglp030 function l16 nc l17 nc m1 nc m2 vccib3 m3 io100rsb3 m4 io98rsb3 m5 io93rsb3 m6 io97rsb3 m7 nc m8 nc m9 io71rsb2 m10 nc m11 io63rsb2 m12 nc m13 io57rsb1 m14 nc m15 nc m16 nc m17 vccib1 n1 nc n2 nc n3 io95rsb3 n4 io96rsb3 n5 gnd n6 nc n7 io85rsb2 n8 io79rsb2 n9 io77rsb2 n10 vccib2 n11 nc n12 nc n13 io59rsb2 n14 nc n15 gnd n16 io56rsb1 n17 io55rsb1 p1 io94rsb3 289-pin csp pin number aglp030 function
igloo plus low power flash fpgas revision 11 3-19 p2 nc p3 gnd p4 nc p5 nc p6 io87rsb2 p7 io80rsb2 p8 gnd p9 io72rsb2 p10 io67rsb2 p11 io61rsb2 p12 nc p13 vccib2 p14 nc p15 io60rsb2 p16 io62rsb2 p17 vjtag r1 gnd r2 io91rsb2 r3 nc r4 nc r5 nc r6 vccib2 r7 io83rsb2 r8 io78rsb2 r9 io74rsb2 r10 io70rsb2 r11 gnd r12 nc r13 nc r14 nc r15 nc r16 tms r17 trst t1 io92rsb3 t2 io89rsb2 t3 nc t4 gnd 289-pin csp pin number aglp030 function t5 nc t6 io84rsb2 t7 io81rsb2 t8 io76rsb2 t9 vccib2 t10 io69rsb2 t11 io65rsb2 t12 io64rsb2 t13 nc t14 gnd t15 nc t16 tdi t17 tdo u1 ff/io90rsb2 u2 gnd u3 nc u4 io88rsb2 u5 io86rsb2 u6 io82rsb2 u7 gnd u8 io75rsb2 u9 io73rsb2 u10 io68rsb2 u11 io66rsb2 u12 gnd u13 nc u14 nc u15 nc u16 tck u17 vpump 289-pin csp pin number aglp030 function
package pin assignments 3-20 revision 11 289-pin csp pin number aglp060 function a1 gab1/io03rsb0 a2 nc a3 nc a4 gnd a5 io10rsb0 a6 io14rsb0 a7 io16rsb0 a8 io18rsb0 a9 gnd a10 io23rsb0 a11 io27rsb0 a12 nc a13 nc a14 gnd a15 nc a16 nc a17 gbc0/io30rsb0 b1 gaa1/io01rsb0 b2 gnd b3 nc b4 nc b5 io07rsb0 b6 nc b7 vccib0 b8 io17rsb0 b9 io19rsb0 b10 io24rsb0 b11 io28rsb0 b12 vccib0 b13 nc b14 nc b15 nc b16 gbc1/io31rsb0 b17 gnd c1 io155rsb3 c2 gaa0/io00rsb0 c3 gac0/io04rsb0 c4 nc c5 vccib0 c6 io09rsb0 c7 io13rsb0 c8 io15rsb0 c9 io21rsb0 c10 gnd c11 io29rsb0 c12 nc c13 nc c14 nc c15 gnd c16 gba0/io34rsb0 c17 io39rsb1 d1 io150rsb3 d2 io151rsb3 d3 gnd d4 gab0/io02rsb0 d5 nc d6 nc d7 nc d8 gnd d9 io20rsb0 d10 io25rsb0 d11 nc d12 nc d13 gnd d14 gbb0/io32rsb0 d15 gba1/io35rsb0 d16 io37rsb1 d17 io42rsb1 e1 vccib3 e2 io147rsb3 e3 gac2/io152rsb3 e4 gaa2/io156rsb3 e5 gac1/io05rsb0 e6 nc e7 io06rsb0 e8 io11rsb0 289-pin csp pin number aglp060 function e9 io22rsb0 e10 io26rsb0 e11 vccib0 e12 nc e13 gbb1/io33rsb0 e14 gba2/io36rsb1 e15 gbb2/io38rsb1 e16 vccib1 e17 io44rsb1 f1 gfc1/io140rsb3 f2 io142rsb3 f3 io149rsb3 f4 vccib3 f5 gab2/io154rsb3 f6 io153rsb3 f7 nc f8 io08rsb0 f9 io12rsb0 f10 nc f11 nc f12 nc f13 gbc2/io40rsb1 f14 gnd f15 io43rsb1 f16 io46rsb1 f17 io45rsb1 g1 gfc0/io139rsb3 g2 gnd g3 io144rsb3 g4 io145rsb3 g5 io146rsb3 g6 io148rsb3 g7 gnd g8 gnd g9 vcc g10 gnd g11 gnd g12 io48rsb1 289-pin csp pin number aglp060 function
igloo plus low power flash fpgas revision 11 3-21 g13 io41rsb1 g14 io47rsb1 g15 io49rsb1 g16 io50rsb1 g17 gnd h1 vcomplf h2 gfb0/io137rsb3 h3 nc h4 io141rsb3 h5 io143rsb3 h6 gfb1/io138rsb3 h7 gnd h8 gnd h9 gnd h10 gnd h11 gnd h12 gcc1/io52rsb1 h13 io51rsb1 h14 gca0/io57rsb1 h15 vccib1 h16 gca2/io58rsb1 h17 gcc0/io53rsb1 j1 vccplf j2 gfa1/io136rsb3 j3 vccib3 j4 io131rsb3 j5 io130rsb3 j6 io129rsb3 j7 vcc j8 gnd j9 gnd j10 gnd j11 vcc j12 gcb2/io59rsb1 j13 gcb1/io54rsb1 j14 io62rsb1 j15 io63rsb1 j16 gcb0/io55rsb1 289-pin csp pin number aglp060 function j17 gca1/io56rsb1 k1 gnd k2 gfa0/io135rsb3 k3 gfb2/io133rsb3 k4 io128rsb3 k5 io123rsb3 k6 io125rsb3 k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 io64rsb1 k13 io61rsb1 k14 io66rsb1 k15 io65rsb1 k16 gnd k17 gcc2/io60rsb1 l1 gfa2/io134rsb3 l2 gfc2/io132rsb3 l3 io127rsb3 l4 gnd l5 io121rsb3 l6 gec1/io116rsb3 l7 gnd l8 gnd l9 vcc l10 gnd l11 gnd l12 gdc1/io72rsb1 l13 gdb1/io74rsb1 l14 vccib1 l15 io70rsb1 l16 io68rsb1 l17 io67rsb1 m1 io126rsb3 m2 vccib3 m3 io124rsb3 289-pin csp pin number aglp060 function m4 io122rsb3 m5 geb0/io113rsb3 m6 geb1/io114rsb3 m7 nc m8 nc m9 io90rsb2 m10 nc m11 io83rsb2 m12 nc m13 gda1/io76rsb1 m14 gda0/io77rsb1 m15 io71rsb1 m16 io69rsb1 m17 vccib1 n1 io119rsb3 n2 io120rsb3 n3 gec0/io115rsb3 n4 gea0/io111rsb3 n5 gnd n6 nc n7 io104rsb2 n8 io98rsb2 n9 io96rsb2 n10 vccib2 n11 nc n12 nc n13 gdb2/io79rsb2 n14 nc n15 gnd n16 gdb0/io75rsb1 n17 gdc0/io73rsb1 p1 io118rsb3 p2 io117rsb3 p3 gnd p4 nc p5 nc p6 io106rsb2 p7 io99rsb2 289-pin csp pin number aglp060 function
package pin assignments 3-22 revision 11 p8 gnd p9 io91rsb2 p10 io86rsb2 p11 io81rsb2 p12 nc p13 vccib2 p14 nc p15 gda2/io78rsb2 p16 gdc2/io80rsb2 p17 vjtag r1 gnd r2 gea2/io110rsb2 r3 nc r4 nc r5 nc r6 vccib2 r7 io102rsb2 r8 io97rsb2 r9 io93rsb2 r10 io89rsb2 r11 gnd r12 nc r13 nc r14 nc r15 nc r16 tms r17 trst t1 gea1/io112rsb3 t2 gec2/io108rsb2 t3 nc t4 gnd t5 nc t6 io103rsb2 t7 io100rsb2 t8 io95rsb2 t9 vccib2 t10 io88rsb2 t11 io84rsb2 289-pin csp pin number aglp060 function t12 io82rsb2 t13 nc t14 gnd t15 nc t16 tdi t17 tdo u1 ff/geb2/io109rs b2 u2 gnd u3 nc u4 io107rsb2 u5 io105rsb2 u6 io101rsb2 u7 gnd u8 io94rsb2 u9 io92rsb2 u10 io87rsb2 u11 io85rsb2 u12 gnd u13 nc u14 nc u15 nc u16 tck u17 vpump 289-pin csp pin number aglp060 function
igloo plus low power flash fpgas revision 11 3-23 289-pin csp pin number aglp125 function a1 gab1/io03rsb0 a2 io11rsb0 a3 io08rsb0 a4 gnd a5 io19rsb0 a6 io24rsb0 a7 io26rsb0 a8 io30rsb0 a9 gnd a10 io35rsb0 a11 io38rsb0 a12 io40rsb0 a13 io42rsb0 a14 gnd a15 io48rsb0 a16 io54rsb0 a17 gbc0/io57rsb0 b1 gaa1/io01rsb0 b2 gnd b3 io06rsb0 b4 io13rsb0 b5 io15rsb0 b6 io21rsb0 b7 vccib0 b8 io28rsb0 b9 io31rsb0 b10 io37rsb0 b11 io39rsb0 b12 vccib0 b13 io44rsb0 b14 io46rsb0 b15 io49rsb0 b16 gbc1/io58rsb0 b17 gnd c1 io210rsb3 c2 gaa0/io00rsb0 c3 gac0/io04rsb0 c4 io09rsb0 c5 vccib0 c6 io17rsb0 c7 io23rsb0 c8 io27rsb0 c9 io33rsb0 c10 gnd c11 io43rsb0 c12 io45rsb0 c13 io50rsb0 c14 io52rsb0 c15 gnd c16 gba0/io61rsb0 c17 io68rsb1 d1 io204rsb3 d2 io205rsb3 d3 gnd d4 gab0/io02rsb0 d5 io07rsb0 d6 io10rsb0 d7 io18rsb0 d8 gnd d9 io34rsb0 d10 io41rsb0 d11 io47rsb0 d12 io55rsb0 d13 gnd d14 gbb0/io59rsb0 d15 gba1/io62rsb0 d16 io66rsb1 d17 io70rsb1 e1 vccib3 e2 io200rsb3 e3 gac2/io207rsb3 e4 gaa2/io211rsb3 e5 gac1/io05rsb0 e6 io12rsb0 e7 io16rsb0 e8 io22rsb0 289-pin csp pin number aglp125 function e9 io32rsb0 e10 io36rsb0 e11 vccib0 e12 io56rsb0 e13 gbb1/io60rsb0 e14 gba2/io63rsb1 e15 gbb2/io65rsb1 e16 vccib1 e17 io73rsb1 f1 gfc1/io194rsb3 f2 io196rsb3 f3 io202rsb3 f4 vccib3 f5 gab2/io209rsb3 f6 io208rsb3 f7 io14rsb0 f8 io20rsb0 f9 io25rsb0 f10 io29rsb0 f11 io51rsb0 f12 io53rsb0 f13 gbc2/io67rsb1 f14 gnd f15 io75rsb1 f16 io71rsb1 f17 io77rsb1 g1 gfc0/io193rsb3 g2 gnd g3 io198rsb3 g4 io203rsb3 g5 io201rsb3 g6 io206rsb3 g7 gnd g8 gnd g9 vcc g10 gnd g11 gnd g12 io72rsb1 289-pin csp pin number aglp125 function
package pin assignments 3-24 revision 11 g13 io64rsb1 g14 io69rsb1 g15 io78rsb1 g16 io76rsb1 g17 gnd h1 vcomplf h2 gfb0/io191rsb3 h3 io195rsb3 h4 io197rsb3 h5 io199rsb3 h6 gfb1/io192rsb3 h7 gnd h8 gnd h9 gnd h10 gnd h11 gnd h12 gcc1/io79rsb1 h13 io74rsb1 h14 gca0/io84rsb1 h15 vccib1 h16 gca2/io85rsb1 h17 gcc0/io80rsb1 j1 vccplf j2 gfa1/io190rsb3 j3 vccib3 j4 io185rsb3 j5 io183rsb3 j6 io181rsb3 j7 vcc j8 gnd j9 gnd j10 gnd j11 vcc j12 gcb2/io86rsb1 j13 gcb1/io81rsb1 j14 io90rsb1 j15 io89rsb1 j16 gcb0/io82rsb1 289-pin csp pin number aglp125 function j17 gca1/io83rsb1 k1 gnd k2 gfa0/io189rsb3 k3 gfb2/io187rsb3 k4 io179rsb3 k5 io175rsb3 k6 io177rsb3 k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 io88rsb1 k13 io94rsb1 k14 io95rsb1 k15 io93rsb1 k16 gnd k17 gcc2/io87rsb1 l1 gfa2/io188rsb3 l2 gfc2/io186rsb3 l3 io182rsb3 l4 gnd l5 io173rsb3 l6 gec1/io170rsb3 l7 gnd l8 gnd l9 vcc l10 gnd l11 gnd l12 gdc1/io99rsb1 l13 gdb1/io101rsb1 l14 vccib1 l15 io98rsb1 l16 io92rsb1 l17 io91rsb1 m1 io184rsb3 m2 vccib3 m3 io176rsb3 289-pin csp pin number aglp125 function m4 io172rsb3 m5 geb0/io167rsb3 m6 geb1/io168rsb3 m7 io159rsb2 m8 io161rsb2 m9 io135rsb2 m10 io128rsb2 m11 io121rsb2 m12 io113rsb2 m13 gda1/io103rsb1 m14 gda0/io104rsb1 m15 io97rsb1 m16 io96rsb1 m17 vccib1 n1 io180rsb3 n2 io178rsb3 n3 gec0/io169rsb3 n4 gea0/io165rsb3 n5 gnd n6 io156rsb2 n7 io148rsb2 n8 io144rsb2 n9 io137rsb2 n10 vccib2 n11 io119rsb2 n12 io111rsb2 n13 gdb2/io106rsb2 n14 io109rsb2 n15 gnd n16 gdb0/io102rsb1 n17 gdc0/io100rsb1 p1 io174rsb3 p2 io171rsb3 p3 gnd p4 io160rsb2 p5 io157rsb2 p6 io154rsb2 p7 io152rsb2 289-pin csp pin number aglp125 function
igloo plus low power flash fpgas revision 11 3-25 p8 gnd p9 io132rsb2 p10 io125rsb2 p11 io126rsb2 p12 io112rsb2 p13 vccib2 p14 io108rsb2 p15 gda2/io105rsb2 p16 gdc2/io107rsb2 p17 vjtag r1 gnd r2 gea2/io164rsb2 r3 io158rsb2 r4 io155rsb2 r5 io150rsb2 r6 vccib2 r7 io145rsb2 r8 io141rsb2 r9 io134rsb2 r10 io130rsb2 r11 gnd r12 io118rsb2 r13 io116rsb2 r14 io114rsb2 r15 io110rsb2 r16 tms r17 trst t1 gea1/io166rsb3 t2 gec2/io162rsb2 t3 io153rsb2 t4 gnd t5 io147rsb2 t6 io143rsb2 t7 io140rsb2 t8 io139rsb2 t9 vccib2 t10 io131rsb2 t11 io127rsb2 289-pin csp pin number aglp125 function t12 io124rsb2 t13 io122rsb2 t14 gnd t15 io115rsb2 t16 tdi t17 tdo u1 ff/geb2/io163rs b2 u2 gnd u3 io151rsb2 u4 io149rsb2 u5 io146rsb2 u6 io142rsb2 u7 gnd u8 io138rsb2 u9 io136rsb2 u10 io133rsb2 u11 io129rsb2 u12 gnd u13 io123rsb2 u14 io120rsb2 u15 io117rsb2 u16 tck u17 vpump 289-pin csp pin number aglp125 function

revision 11 4-1 4 ? datasheet information list of changes the following table lists critical changes that were made in each revision of the igloo plus datasheet. revision changes page revision 11 (jun 2009) the versioning system for datasheets has been changed. datasheets are assigned a revision number that incremen ts each time the datasheet is revised. the "igloo plus device status" table indicates the status for each device in the family. n/a the "reprogrammable flash technology" section was revised to add "250 mhz (1.5 v systems) and 160 mhz (1.2 v systems) system performance." i the "i/os with advanced i/o standards" section was revised to add definitions for hot-swap and cold-sparing. 1-7 conditional statements regarding hot insertion were removed from the description of vi in table 2-1 ? absolute maximum ratings , since all igloo plus devices are hot insertion enabled. 2-1 table 2-2 ? recommended operating conditions1,2 was revised. 1.2 v dc wide range supply voltage and 3.3 v wide range supply voltage (sar 26270) were added for vcci. vjtag dc voltage was revised (sar 24052). the value range for vpump programming voltage for operation was changed from "0 to 3.45" to "0 to 3.6" (sar 25220). 2-2 table 2-6 ? temperature and voltage derating factors for timing delays (normalized to tj = 70c, vcc = 1.425 v) and table 2-7 ? temperature and voltage derating factors for timing delays (normalized to tj = 70c, vcc = 1.14 v) were revised. 2-6 , 2-7 table 2-8 ? power supply state per mode is new. 2-7 the tables in the "quiescent supply current" section were updated (sars 24882 and 24112). some of the table notes were changed or deleted. 2-7 vih maximum values in tables were updated as needed to 3.6 v (sar 20990 and sar 79370 ). n/a
datasheet information 4-2 revision 11 revision 11 (continued) the values in the following tables were updated. 3.3 v lvcmos and 1.2 v lvcmos wide range were added to the tables where applicable. table 2-13 ? summary of i/o input buffer power (per pin) ? default i/o software settings table 2-14 ? summary of i/o output buffer power (per pin) ? default i/o software settings1 table 2-21 ? summary of maximum and minimum dc input and output levels applicable to commercial and industri al conditions?software default settings table 2-22 ? summary of maximu m and minimum dc input levels table 2-23 ? summary of ac measuring points table 2-25 ? summary of i/o timing charac teristics?software default settings, std speed grade, commercial-case conditions: tj = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v table 2-26 ? summary of i/o timing charac teristics?software default settings, std speed grade commercial-case conditions: tj = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v table 2-28 ? i/o output bu ffer maximum resistances 1 2-9 2-9 2-19 2-20 2-21 2-22 2-23 2-24 a table note was added to table 2-16 ? different components contributing to the static power consumption in igloo plus devices and table 2-18 ? different components contributing to the static power consumption in igloo plus devices stating the value for pdc4 is the minimum contribution of the pll when operating at lowest frequency. 2-11 , 2-12 table 2-29 ? i/o weak pull-up/pull-down resistances was revised, including addition of 3.3 v and 1.2 v lvcmos wide range. the notes defining r weak pull- up-max and r weak pulldown-max were revised (sar 21348). 2-25 table 2-30 ? i/o short currents iosh/iosl was revised to include data for 3.3 v and 1.2 v lvcmos wide range (sar 79353 and sar 79366). 2-25 table 2-31 ? duration of shor t circuit event before failure was revised to change the maximum temperature fr om 110c to 100c, with an example of six months instead of three months (sar 26259). 2-26 the tables in the "single-ended i/o char acteristics" section were updated. notes clarifying i il and i ih were added. tables for 3.3 v lvcmos and 1.2 v lvcmos wide range were added (sar 79370, sar 79353, and sar 79366 ). notes in the wide range tables state that the minimum drive strength for any lvcmos 3.3 v (or lvcmos 1.2 v) software configuration when run in wide range is 100 a. drive strength displa yed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models (sar 25700). 2-27 the following sentence was deleted from the "2.5 v lvcmos" section : it uses a 5 v?tolerant input buffer and push -pull output buffer (sar 24916). 2-32 the tables in the "input register" section , "output register" section , and "output enable register" section were updated. the tables in the "versatile characteristics" section were updated. 2-45 through 2-56 revision changes page
igloo plus low power flash fpgas revision 11 4-3 revision 11 (continued) the following tables were updated in the "global tree timing characteristics" section : table 2-85 ? aglp060 global resource (1.5 v) table 2-86 ? aglp125 global resource (1.5 v) table 2-88 ? aglp060 global resource (1.2 v) 2-58 table 2-90 ? igloo plus ccc/pll specification and table 2-91 ? igloo plus ccc/pll specification were revised (sar 79388). vco output jitter and maximum peak-to-peak jitter data were changed. three notes were added to the table in connection with these changes. 2-61 figure 2-28 ? write access after write onto same address and figure 2-29 ? write access after read onto same address were deleted. n/a the tables in the "sram" , "fifo" and "embedded flashrom characteristics" sections were updated. 2-68 , 2-77 revision 10 (apr 2009) product brief v1.5 dc and switching characteristics advance v0.5 the ?f speed grade is no longer offered for igloo plus devices. references to it have been removed from the document. the speed grade column and note regarding ?f speed grade were removed from "igloo plus ordering information" . the "speed grade and temperature grade matrix" section was removed. iii , iv revision 9 (feb 2009) product brief v1.4 the "advanced i/o" section was revised to add two bullets regarding support of wide range power supply voltage. i the "i/os with advanced i/o standards" section was revised to add 3.0 v wide range to the list of supported voltages. the "wide range i/o support" section is new. 1-7 revision 8 (jan 2009) packaging v1.5 the "201-pin csp" pin table was revised to add a note regarding pins g1 and h1. 3-8 revision 7 (dec 2008) product brief v1.3 a note was added to igloo plus devices : "aglp060 in cs201 does not support the pll." i table 2 ? igloo plus fpgas package size dimensions was updated to change the nominal size of vq176 from 100 to 400 mm 2 . ii revision 6 (oct 2008) dc and switching characteristics advance v0.4 data was revised significantly in the following tables: table 2-25 ? summary of i/o timing charac teristics?software default settings, std speed grade, commercial-case conditions: tj = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v table 2-26 ? summary of i/o timing charac teristics?software default settings, std speed grade commercial-case conditions: tj = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v table 2-50 ? 2.5 lvcmos low slew ? applies to 1.2 v dc core voltage table 2-51 ? 2.5 v lvcmos high slew ? applies to 1.2 v dc core voltage 2-22 , 2-33 revision 5 (aug 2008) product brief v1.2 the vq128 and vq176 packages were added to table 1 ? igloo plus product family , the "i/os per package 1" table, table 2 ? igloo plus fpgas package size dimensions , "igloo plus ordering information" , and the "temperature grade offerings" table. i to iv packaging v1.4 the "128-pin vqfp" package drawing and pin table are new. 3-2 the "176-pin vqfp" package drawing and pin table are new. 3-5 revision changes page
datasheet information 4-4 revision 11 revision 4 (jul 2008) product brief v1.1 dc and switching characteristics advance v0.3 as a result of the libero ide v8.4 release, actel now offers a wide range of core voltage support. the document was updated to change 1.2 v / 1.5 v to 1.2 v to 1.5 v. n/a revision 3 (jun 2008) dc and switching characteristics advance v0.2 tables have been updated to reflect default values in the software. the default i/o capacitance is 5 pf. tables have been updated to include the lvcmos 1.2 v i/o set. n/a table note 3 was updated in table 2-2 ? recommended operating conditions1,2 to add the sentence, "v cci should be at the same voltage within a given i/o bank." references to table notes 5, 6, 7, and 8 were added. reference to table note 3 was removed from v pump operation and placed next to v cc . 2-2 table 2-4 ? overshoot and undershoot limits 1 was revised to remove "as measured on quiet i/os" from the title. table note 2 was revised to remove "estimated sso density over cycles." table note 3 was deleted. 2-3 the table note for table 2-9 ? quiescent supply current (idd) characteristics, igloo plus flash*freeze mode* to remove the sentence stating that values do not include i/o static contribution. 2-7 the table note for table 2-10 ? quiescent supply current (idd) characteristics, igloo plus sleep mode* was updated to remove v jtag and v cci and the statement that values do not include i/o static contribution. 2-7 the table note for table 2-11 ? quiescent supply current (idd) characteristics, igloo plus shutdown mode was updated to remove t he statement that values do not include i/o static contribution. 2-8 note 2 of table 2-12 ? quiescent supply current (idd), no igloo plus flash*freeze mode 1 was updated to include v ccpll . table note 4 was deleted. 2-8 table 2-13 ? summary of i/o input buffer power (per pin) ? default i/o software settings and table 2-14 ? summary of i/o output buffer power (per pin) ? default i/o software settings1 were updated to remove static power. the table notes were updated to reflect that power was measured on v cci . table note 2 was added to table 2-13 ? summary of i/o input buff er power (per pin) ? default i/o software settings . 2-9 , 2-9 table 2-16 ? different components contribut ing to the static power consumption in igloo plus devices and table 2-18 ? different components contributing to the static power consumption in igloo plus devices were updated to change the definition for p dc5 from bank static power to bank quiescent power. table subtitles were added for table 2-16 ? different components contributing to the static power consumption in igloo plus devices , table 2-17 ? different components contributing to dynamic power consumption in igloo plus devices , and table 2-18 ? different components contributing to the static power consumption in igloo plus devices . 2-11 , 2-12 the "total static power consumption?pstat" section was revised. 2-12 table 2-32 ? schmitt trigger input hysteresis is new. 2-26 packaging v1.3 the "281-pin csp" package drawing is new. 3-13 the "281-pin csp" table for the aglp125 device is new. 3-13 revision changes page
igloo plus low power flash fpgas revision 11 4-5 revision 3 (continued) the "289-pin csp" package drawing was incorrect. the graphic was showing the cs281 mechanical drawing and not the cs289 mechanical drawing. this has now been corrected. 3-17 revision 2 (jun 2008) packaging v1.2 the "289-pin csp" table for the aglp030 device is new. 3-17 revision 1 (jun 2008) packaging v1.1 the "289-pin csp" table for the aglp060 device is new. 3-20 the "289-pin csp" table for the aglp125 device is new. 3-23 revision changes page
datasheet information 4-6 revision 11 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "igloo plus device" table on page ii , is designated as ei ther "product brief," "advance," "preliminary," or "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status document may not have completed actel?s qualification process. actel may amend or enhanc e products during the pr oduct introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any actel pr oduct (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult actel?s terms and conditions for specific liab ility exclusions relating to life-support applications. a reliability report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for additional reliability information.

actel is the leader in low power fpgas and mixed signal fpgas and offers the most comprehensive portfolio of system and power management solutions. power matters. learn more at www.actel.com. actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court,meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu buillding 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn 51700102-11/6.10 ? actel corporation. all rights reserved. actel, actel fusion, igloo, libero, pigeon point, pro asic, smartfusion and the associ ated logos are trademarks or registered trademarks of actel corporation. all other trademarks and service marks are the property of their resp ective owners.

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